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ICS85222I-02

1-to-2, LVCMOS/LVTTL- To- Differential HSTL Translator

Integrated Device Technology 

ICS85222I-02 Data Sheet

1-TO-2, LVCMOS/LVTTL -TO- DIFFERENTIAL HSTL TRANSLATOR

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS85222I-02.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS85222I-02 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW

• Power (outputs)MAX = 82.3mW/Loaded Output pair

If all outputs are loaded, the total power is 2 x 82.3mW = 164.6mW

Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 164.6mW = 337.85mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C.

The equation for Tj is as follows: Tj = JA * Pd_total + TA

Tj = Junction Temperature

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 103°C/W per Table 5 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.338W * 103°C/W = 119.8°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (single layer or multi-layer).

Table 5. Thermal Resitance JA for 8-Lead SOIC, Forced Convection

JA by Velocity

Meters per Second

0

Multi-Layer PCB, JEDEC Standard Test Boards

103°C/W

1

94°C/W

2.5

89°C/W

ICS85222AMI-02 APRIL 25, 2014

7

©2014 Integrated Device Technology, Inc.

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