74V2G132 Просмотр технического описания (PDF) - STMicroelectronics

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74V2G132

DUAL 2-INPUT SHMITT TRIGGER NAND GATE

STMicroelectronics 

74V2G132

DUAL 2-INPUT SHMITT TRIGGER NAND GATE

s HIGH SPEED: tPD = 3.0ns (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 1µA(MAX.) at TA=25°C

s TYPICAL HYSTERESIS:

VH = 800mV at VCC = 4.5V

VH = 500mV at VCC = 3.0V

s POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8mA (MIN) at VCC = 4.5V

IIOH| = IOL = 4mA (MIN) at VCC = 3.0V

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 5.5V

s IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74V2G132 is an advanced high-speed CMOS

SINGLE 2-INPUT NAND GATE fabricated with

sub-micron silicon gate and double-layer metal

wiring C2MOS tecnology.

Pin configuration and function are the same as

those of the 74V2G00 but the 74V2G132 has

hysteresis.

PRELIMINARY DATA

SOT23-8L

SOT323-8L

ORDER CODES

PACKAGE

SOT23-8L

SOT323-8L

T&R

74V2G132STR

74V2G132CTR

The internal circuit is composed of 3 stages

including buffer output, which provide high noise

immunity and stable output.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

PIN CONNECTION AND IEC LOGIC SYMBOLS

November 2001

1/9

This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.

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