CXD3511 Просмотр технического описания (PDF) - Sony Semiconductor

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CXD3511

Digital Signal Driver/Timing Generator

Sony Semiconductor 

CXD3511Q

(n) Selectable delay line block

This block supports signal shifting in 1-dot units, performs signal port switching linked with right/left inversion

and signal processing that supports dot/line inversion.

This block is comprised of five selectors: dot shift selector, right/left inversion selector, dot/line selector, up/

down inversion pre-selector, and up/down inversion post-selector.

The delay line size is 1200 words.

The data paths for this block are shown in the figure below. Port switching during right/left inversion depends

on the Cond1 value, and port switching during up/down inversion (when dot/line inversion support is ON)

depends on the Cond2 value.

Cond1 = (RGT_SEL_ON) AND [(RGT) Ex-NOR (DLY_R (G, B)_RGT)]

Cond2 = (DWN) Ex-NOR (DLY_DWN)

Note) RGT and DWN are TG block settings.

Input port 1

Input port 2

Dot shift

selector

HP[0]

Right/left

inversion

selector

Cond1

Dot/line

selector

DLY_ON

Up/down

inversion

pre-selector

Cond2

Delay line

Up/down

inversion

post-selector

Cond2

Output port 1

Output port 2

Solid lines: 1

Dotted lines: 0

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