LTC1403-1 Просмотр технического описания (PDF) - Linear Technology

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LTC1403-1

Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown

Linear Technology 

LTC1407-1/LTC1407A-1

APPLICATIO S I FOR ATIO

5V

C5

0.1µF

VIN

1.25VP-P

MAX

–

U1

1+/2 LT1819

C6

0.1µF

R4

R3

499Ω 499Ω –5V

–

U2

1+/2 LT1819

C3

1µF R1

51Ω

C1

47pF

R5

1k

1.5VCM

R6

1k

C4

1µF R2

51Ω

C2

47pF

+CH0 OR

+CH1

LTC1407A-1

–CH0 OR

–CH1

1407A F06a

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

185k

371k

556k

741k

FREQUENCY (Hz)

14031 F06b

Figure 6b. LTC1407-1 6MHz Sine Wave 4096 Point FFT Plot

with the LT1819 Driving the Inputs Differentially

Figure 6a. The LT1819 Driving the LTC1407A-1 Differentially

Board Layout and Bypassing

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performance from the LTC1407-1/LTC1407A-1, a printed

circuit board with ground plane is required. Layout for the

printed circuit board should ensure that digital and analog

signal lines are separated as much as possible. In particu-

lar, care should be taken not to run any digital track

alongside an analog signal track. If optimum phase match

between the inputs is desired, the length of the four input

wires of the two input channels should be kept matched.

But each pair of input wires to the two input channels

should be kept separated by a ground trace to avoid high

frequency crosstalk between channels.

High quality tantalum and ceramic bypass capacitors should

be used at the VDD and VREF pins as shown in the Block

Diagram on the first page of this data sheet. For optimum

performance, a 10µF surface mount tantalum capacitor

with a 0.1µF ceramic is recommended for the VDD and VREF

pins. Alternatively, 10µF ceramic chip capacitors such as

X5R or X7R may be used. The capacitors must be located

as close to the pins as possible. The traces connecting the

pins and the bypass capacitors must be kept short and

should be made as wide as possible. The VDD bypass ca-

pacitor returns to GND (Pin 6) and the VREF bypass capaci-

tor returns to the Exposed Pad ground (Pin 11). Care should

Figure 7. Recommended Layout

1407-1 F07

be taken to place the 0.1µF VDD bypass capacitor as close

to Pins 6 and 7 as possible.

Figure 7 shows the recommended system ground connec-

tions. All analog circuitry grounds should be terminated at

14071f

15

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