MT90863(2000) Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT90863
(Rev.:2000)

3V Rate Conversion Digital Switch

Zarlink Semiconductor Inc 

MT90863 Advance Information

Read/Write Address:

Reset Value:

03H,

0000H.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FE4 FE3 FE2 FE1 FE0 CFE FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0

Bit

15-11

10

9

8-0

Name

FE4-0

CFE

FD9

FD8-0

Description

Frame Evaluation Input Select. The binary value expressed in these bits refers

to the frame evaluation inputs, FEi0 to FEi23.

Complete Frame Evaluation. When CFE = 1, the frame evaluation is completed

and bits FD9 to FD0 bits contains a valid frame alignment offset. This bit is reset to

zero, when SFE bit in the IMS register is changed from 1 to 0. This bit is read-only.

Frame Delay Bit 11. The falling edge of FE is sampled during the CLK-high phase

(FD9 = 1) or during the CLK-low phase (FD9 = 0). This bit allows the

measurement resolution to 1/2 CLK cycle. This bit is read-only.

Frame Delay Bits. The binary value expressed in these bits refers to the

measured input offset value. These bits are reset to zero when the SFE bit of the

IMS register changes from 1 to 0. (FD8 = MSB, FD0 = LSB). These bits are also

read-only

Table 9 - Frame Alignment (FAR) Register Bit

ST-BUS F0i

C16i

Offset Value

FEi Input

C4i

HMVIP F0i

C16i

Offset Value

FEi Input

16

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

(FD[8:0] = 06H)

(FD9 = 0, sample at CLK low phase)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

(FD[8:0] = 08H)

(FD9 = 1, sample at CLK high phase)

Figure 8 - Example for Frame Alignment Measurement

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