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MPC7410PEPNS

MPC7410 RISC Microprocessor Hardware Specifications

Unspecified 

Revision

1.0

Date

—

Document Revision History

Table 16. Document Revision History (continued)

Substantive Change(s)

Section 1.3 and Table 3—revised OVDD from 3.3 V ± 100 mV to 3.3 V ± 165 mV.

Table 13—removed unsupported PLL configurations.

Table 12—added note 15 for minimum MCP pulse width, correct note 3 for 3.3-V processor bus

support.

Table 13—revised note 3 to include emulator tool development.

Table 14—removed unsupported Core-to-L2 example frequencies.

Section 1.8.8—updated heat sink vendors list.

Section 1.8.8.2—updated interface vendors list.

Table 1—updated voltage sequencing requirements notes 3 and 4.

Table 4—Updated/added thermal characteristics.

Table 5—removed table and TAU related information, TAU is no longer supported.

Table 6—updated Iin and ITSI leakage current specs.

Section 1.8.3—removed section.

Section 1.10—reformatted section.

Section 1.8.6—changed recommended pull-up resistor value to 1 kW–5 kW. Added AACK, TEA, and

TS to control signals needing pull-ups. Added pull-up resistor value recommendation for

L1_TSTCLK, L2_TSTCLK, and LSSD_MODE factory test signals.

Section 1.8.7—revised text regarding connection of TRST. Combined Figure 22, Figure 23, and Table

17, into Figure 21.

Table 7—corrected min VCO frequencies from 450 to 700 MHz to match min processor frequency of

350 MHz.

Table 2—added note 3 to clarify BVSEL for revisions prior to Rev. E which do not support 3.3 V OVDD.

Table 3—added notes 5 and 6 to clarify BVSEL for revisions prior to Rev. E which do not support 3.3 V

OVDD.

Table 5—added note 8 regarding DC voltage limits for JTAG signals.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

51

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