ISL59444 Просмотр технического описания (PDF) - Renesas Electronics
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ISL59444 Datasheet PDF : 13 Pages
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ISL59444
Pin Configuration
ISL59444 (16 LD SO)
TOP VIEW
IN0 1
NIC 2
IN1 3
GND 4
IN2 5
NIC 6
IN3 7
NIC 8
16 V+
15 S0
14 S1
13 HIZ
12 OUT
11 LE2
10 LE1
9 V-
Pin Descriptions
PIN NUMBER
1
2, 6, 8
3
4
5
7
9
10
PIN NAME
IN0
NIC
IN1
GND
IN2
IN3
V-
LE1
11
LE2
12
OUT
13
HIZ
14
S1
EQUIVALENT
CIRCUIT
Circuit 1
Circuit 1
Circuit 4
Circuit 1
Circuit 1
Circuit 4
Circuit 2
Circuit 2
Circuit 3
Circuit 2
Circuit 2
DESCRIPTION
Input for channel 0
Not Internally Connected; it is recommended this pin be tied to ground to minimize
crosstalk.
Input for channel 1
Ground pin
Input for channel 2
Input for channel 3
Negative Power Supply
Synchronized channel switching: When LE1 is low, the master control latch loads the
next switching address. The Mux Amp is configured for this address when LE2 goes low.
Synchronized operation results when LE2 is the inverse of LE1. Channel selection is
asynchronous (changes with any control signal change) if both LE1 and LE2 are
both low.
Synchronized channel switching: When LE2 is low, the newly selected channel, stored
in the master latch via LE1 is selected. Synchronized operation results when LE2 is the
inverse of LE1. Channel selection is asynchronous (changes with any control signal
change) if both LE1 and LE2 are both low.
Output
Output disable (active high); there are internal pull-down resistors, so the device will be
active with no connection; “HI” puts the output in high impedance state.
Channel selection pin MSB (binary logic code)
FN7451 Rev 3.00
August 16, 2012
Page 2 of 13
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