Si4136
Control Registers
Table 11. Register Summary
Register Name
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Main
0 0 0 0 AUXSEL IFDIV 0 0 0 XIN LPWR 0 AUTO 0 0 0
Configuration
DIV2
PDB
1 Phase
000 0 0 0 0 0 00 0 0
KPI
Detector
Gain
KP2
KP1
2 Power
Down
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDIB PDRB
3 RF1 N
Divider
NRF1
4 RF2 N
0
Divider
NRF2
5 IF N Divider 0 0
NIF
6 RF1 R
Divider
000 0 0
RRF1
7 RF2 R
Divider
000 0 0
RRF2
8 IF R Divider 0 0 0 0 0
RIF
9 Reserved
.
.
.
15 Reserved
Note: Registers 9–15 are reserved. Writes to these registers may result in unpredictable behavior.
Rev. 1.0
21