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SI4136-BT

ISM RF SYNTHESIZER WITH INTEGRATED VCOS FOR WIRELESS COMMUNICATIONS

Silicon Laboratories 

Si4136

(Register 0) can be set to 1 to reduce the bias currents

and therefore reduce the power dissipated by the IF

amplifier. For loads less than 500 Ω, LPWR should be

set to 0 to maximize the output level.

For IF frequencies greater than 500 MHz, a matching

network is required in order to drive a 50 Ω load. See

Figure 15 below. The value of LMATCH can be

determined by Table 9.

Typical values range between 8 nH and 40 nH.

IFOUT

>500 pF

LMATCH

50 Ω

450

400

350

LPWR=0

300

LPWR=1

250

200

150

100

50

0

0

200

400

600

800

1000

1200

Load Resistance (Ω)

Figure 17. Typical IF Output Voltage vs.

Load Resistance at 550 MHz

Reference Frequency Amplifier

Figure 15. IF Frequencies > 500 MHz

Table 9. LMATCH Values

Frequency

500–600 MHz

600–800 MHz

800–1 GHz

LMATCH

40 nH

27 nH

18 nH

For frequencies less than 500 MHz, the IF output buffer

can directly drive a 200 Ω resistive load or higher. For

resistive loads greater than 500 Ω (f < 500 MHz) the

LPWR bit can be set to reduce the power consumed by

the IF output buffer. See Figure 16 below.

IFOUT

>500 pF

>200 Ω

Figure 16. IF Frequencies < 500 MHz

The Si4136 provides a reference frequency amplifier. If

the driving signal has CMOS levels, it can be connected

directly to the XIN pin. Otherwise, the reference

frequency signal should be AC coupled to the XIN pin

through a 560 pF capacitor.

Power Down Modes

Table 10 summarizes the power down functionality. The

Si4136 can be powered down by taking the PWDNB pin

low or by setting bits in the Power Down register

(Register 2). When the PWDNB pin is low, the Si4136

will be powered down regardless of the Power Down

register settings. When the PWDNB pin is high, power

management is under control of the Power Down

register bits.

The IF and RF sections of the Si4136 circuitry can be

individually powered down by setting the Power Down

register bits PDIB and PDRB low. The reference

frequency amplifier will also be powered up if either the

PDRB and PDIB bits are high. Also, setting the

AUTOPDB bit to 1 in the Main Configuration register

(Register 0) is equivalent to setting both bits in the

Power Down register to 1.

The serial interface remains available and can be

written in all power-down modes.

Auxiliary Output (AUXOUT)

The signal appearing on AUXOUT is selected by setting

the AUXSEL bits in the Main Configuration register

(Register 0).

The LDETB signal can be selected by setting the

AUXSEL bits to 011. This signal can be used to indicate

that the IF or RF PLL is about to lose lock due to

excessive ambient temperature drift and should be re-

tuned.

Rev. 1.0

19

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