CXD3003 Просмотр технического описания (PDF) - Sony Semiconductor

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производитель

CXD3003

CD Digital Signal Processor with Built-in Digital Servo and DAC

Sony Semiconductor 

CXD3003R

Pin Symbol

I/O

No.

Description

123 TRDR O 1, 0 Tracking drive output.

124 FFDR O 1, 0 Focus drive output.

125 FRDR O 1, 0 Focus drive output.

126 DVDD5

Digital power supply.

128 VCOO O 1, 0 Analog EFM PLL oscillation circuit output.

129 VCOI

I

Analog EFM PLL oscillation circuit input. flock = 8.6436MHz

130 TEST

I

Test pin. Normally fixed to low.

131 TES2

I

Test pin. Normally fixed to low.

132 TES3

I

Test pin. Normally fixed to low.

133 PDO

O 1, Z, 0 Analog EFM PLL charge pump output.

134 VCKI

I

Variable pitch clock input from the external VCO. fcenter = 16.9344MHz

Set VCKI to low when the external clock is not input to this pin.

135 V16M O 1, Z, 0 Wide-band EFM PLL VCO2 oscillation output.

136 AVDD2

Analog power supply.

137 IGEN

I

Connects the operational amplifier current source reference resistance connection.

138 AVSS2

Analog GND.

139 ADIO O

Operational amplifier output.

140 RFDC I

RF signal input.

141 CE

I

Center servo analog input.

142 TE

I

Tracking error signal input.

∗ In the CXD3003R, the following pins are NC.

Pins 1, 2, 19, 35, 36, 37, 38, 54, 71, 72, 73, 74, 90, 107, 108, 109, 110, 127, 143 and 144

Notes) • The 64-bit slot is an LSB first, two's complement output. The 48-bit slot is an MSB first, two's

complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before

sync protection.

• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the

EFM signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion protection timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.

• C2PO represents the data error status.

• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.

–8–

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