
VN16118
Figure 1. Functional Block Diagram
EWRAP
TX<9:0>
10
10
Input Data Latch
Shift Registers
TX_CLK
TX PLL Clock
Generator
RX_CLK<1>
RX_CLK<0>
62.5 MHz
÷2
62.5 MHz
10
RX<9:0>
Output Latch
125 MHz
RX PLL Clock
Recovery
EN_CDET
COM_DET
10
FRAME
ENABLE
10
Shift
Registers
Preliminary
DOUT+
DOUT-
DIN+
DIN-
1999-12-15
Page 2
MDSN-0001-00
Vaishali Semiconductor l 747 Camden Avenue l Campbell l CA 95008 l Ph. 408.379.2900 l Fax 408.379.2937