AD5311BRT-REEL Просмотр технического описания (PDF) - Analog Devices
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AD5311BRT-REEL
Analog Devices
AD5311BRT-REEL Datasheet PDF : 16 Pages
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AD5301/AD5311/AD5321
AC CHARACTERISTICS1 VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; All specifications TMIN to TMAX, unless
otherwise noted.
Parameter2
B Version3
Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time
AD5301
AD5311
AD5321
Slew Rate
Major-Code Change Glitch Impulse
Digital Feedthrough
6
8
7
9
8
10
0.7
12
0.3
VDD = 5 V
µs
1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)
µs
1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)
µs
1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)
V/µs
nV-s 1 LSB Change around Major Carry
nV-s
NOTES
1See Terminology section.
2Guaranteed by design and characterization, not production tested.
3Temperature range is as follows: B Version: –40°C to +105°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1
VDD = 2.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Limit at TMIN, TMAX
Parameter2 (B Version)
Unit
Conditions/Comments
fSCL
400
t1
2.5
t2
0.6
t3
1.3
t4
0.6
t5
100
t63
0.9
0
t7
0.6
t8
0.6
t9
1.3
t10
300
0
t11
250
300
20 + 0.1Cb4
Cb
400
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns max
ns min
pF max
SCL Clock Frequency
SCL Cycle Time
tHIGH, SCL High Time
tLOW, SCL Low Time
tHD,STA, Start/Repeated Start Condition Hold Time
tSU,DAT, Data Setup Time
tHD,DAT, Data Hold Time
tSU,STA, Setup Time for Repeated Start
tSU,STO, Stop Condition Setup Time
tBUF, Bus Free Time Between a STOP Condition and a START Condition
tR, Rise Time of Both SCL and SDA when Receiving
May be CMOS Driven
tF, Fall Time of SDA when Receiving
tF, Fall Time of Both SCL and SDA when Transmitting
Capacitive Load for Each Bus Line
NOTES
1See Figure 1.
2Guaranteed by design and characterization, not production tested.
3A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH MIN of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Specifications subject to change without notice.
REV. A
–3–
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