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ICS525-01RIT

OSCaR™ User Configurable Clock

Integrated Device Technology 

ICS525-01/02

OSCaRTM User Configurable Clock

External Components/Crystal

Selection

Decoupling Capacitors

The ICS525-01/02 requries two 0.01µF decoupling

capacitors to be connected between VDD and GND,

one on each side of the chip. The capacitor must be

connected close to the device to minimize lead

inductance. No external power supply filtering is

required for this device.

External Resistors

A 33Ω series terminating resistor can be used next to

the CLK and REF pins.

Crystal Load Capacitors

The approximate total on-chip capacitance for a crystal

is 16 pF, so a parallel resonant, fundamental mode

crystal with this value of load (correlation) capacitance

should be used. For crystals with a specified load

capacitance greater than 16 pF, crystal capacitors may

be connected from each of the pins X1 and X2 to

Ground as shown in the block diagram. The value (in

pF) of these crystal caps should be (CL -16)*2, where

CL is the crystal load capacitance in pF. These external

capacitors are only required for applications where the

exact frequency is critical. For a clock input, connect to

X1 and leave X2 unconnected (no capacitors on

either).

Determining the Output Frequency

Users have full control in setting the desired output

frequency over the range shown in the table on page 2.

To replace a standard oscillator, users should connect

the divider select input pins directly to ground (or VDD,

although this is not required because of internal

pull-ups) during Printed Circuit Board layout. The

ICS525-01/02 will automatically produce the correct

clock when all components are soldered. It is also

possible to connect the inputs to parallel I/O ports to

switch frequencies. By choosing divides carefully, the

number of inputs which need to be changed can be

minimized. Observe the restrictions on allowed values

of VDW and RDW.

ICS525-01 Settings

The output of the ICS525-01 can be determined by the

following simple equation:

CLK Frequency = Input Frequency × 2x (---R-----D(---V-W---D-----+W-----2--+--)---•8----)-O-----D---

Where:

Reference Divider Word (RDW) = 1 to 127 (0 not

permitted)

VCO Divider Word (VDW) = 4 to 511 (0, 1, 2, 3 not

permitted)

Output Divider (OD) = values on page 3

Also, the following operating ranges should be

observed:

30M < Input Frequencyx2x(----V----D-----W-------+-----8----)- < 200M(3.3V)or320M(5v )

(RDW + 2)

200kHz < -I--n---p---(-u--R--t--F-D---r-W--e----q--+-u----2e---)-n----c---y--

See table on page 3 for full details of maximum

output.

ICS525-02 Settings

The output of the ICS525-02 can be determined by the

following simple equation:

CLK Frequency = Input Frequency × 2x (---R-----D(---V-W---D-----+W-----2--+--)---•8----)-O-----D---

Where:

Reference Divider Word (RDW) = 0 to 127

VCO Divider Word (VDW) = 0 to 511

Output Divider (OD) = values on page 3

Also, the following operating ranges should be

observed:

30M < Input Frequencyx2x-(---V----D-----W-------+-----8----)- < 240M(3.3V)or400M(5v )

(RDW + 2)

200kHz < -I--n---p---(-u--R--t--F-D---r-W--e----q--+-u----2e---)-n----c---y--

See table on page 3 for full details of maximum

output.

MDS 525-01/02 R

4

Integrated Device Technology, Inc. ● www.idt.com

Revision 021710

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