AD7533JN_01 Просмотр технического описания (PDF) - Intersil
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AD7533JN_01 Datasheet PDF : 9 Pages
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AD7523, AD7533
Electrical Specifications
PARAMETER
V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, Unless Otherwise Specified (Continued)
AD7523
AD7533
TA 25oC
TA MIN-MAX
TA 25oC
TA MIN-MAX
TEST CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX
UNITS
ANALOG OUTPUT
Output Capacitance
DIGITAL INPUTS
COUT1 All Digital Inputs High (Note 4) -
100
-
100
-
100
-
100
pF
COUT2
-
30
-
30
-
35
-
35
pF
COUT1 All Digital Inputs Low (Note 4) -
30
-
30
-
35
-
35
pF
COUT2
-
100
-
100
-
100
-
100
pF
Low State Threshold, VIL
High State Threshold, VIH
Input Current (Low or High), IIL, IIH VIN = 0V or + 15V
Input Coding
See Tables 1 through 3
-
0.8
-
0.8
-
0.8
-
0.8
V
2,4
-
2,4
-
2.4
-
2.4
-
V
-
±1
-
±1
-
±1
-
±1
µA
Binary/Offset Binary
Binary/Offset Binary
Input Capacitance
(Note 4)
-
4
-
4
-
4
-
4
pF
POWER SUPPLY CHARACTERISTICS
Power Supply Voltage Range
(Note 6)
+5 to +16
+5 to +16
V
I+
All Digital Inputs High or Low -
2
-
2.5
-
2
-
2.5
mA
(Excluding Ladder Network)
NOTES:
2. Full Scale Range (FSR) is 10V for unipolar and ±10V for bipolar modes.
3. Using internal feedback resistor, RFEEDBACK.
4. Guaranteed by design or characterization and not production tested.
5. Accuracy not guaranteed unless outputs at ground potential.
6. Accuracy is tested and guaranteed at V+ = +15V, only.
Definition of Terms
Nonlinearity: Error contributed by deviation of the DAC
transfer function from a “best straight line” through the actual
plot of transfer function. Normally expressed as a
percentage of full scale range or in (sub)multiples of 1 LSB.
Resolution: It is addressing the smallest distinct analog
output change that a D/A converter can produce. It is
commonly expressed as the number of converter bits. A
converter with resolution of n bits can resolve output changes
of 2-N of the full-scale range, e.g., 2-N VREF for a unipolar
conversion. Resolution by no means implies linearity.
Settling Time: Time required for the output of a DAC to
settle to within specified error band around its final value
(e.g., 1/2 LSB) for a given digital input change, i.e., all digital
inputs LOW to HIGH and HIGH to LOW.
Gain Error: The difference between actual and ideal analog
output values at full-scale range, i.e., all digital inputs at
HIGH state. It is expressed as a percentage of full scale
range or in (sub)multiples of 1 LSB.
Feedthrough Error: Error caused by capacitive coupling
from VREF to IOUT1 with all digital inputs LOW.
Output Capacitance: Capacitance from IOUT1 , and IOUT2
terminals to ground.
Output Leakage Current: Current which appears on
IOUT1 , terminal when all digital inputs are LOW or on IOUT2
terminal when all digital inputs are HIGH.
For further information on the use of this device, see the
following Application Notes:
Application Notes
NOTE #
DESCRIPTION
AN002 “Principles of Data Acquisition and Conversion”
AN018 “Do’s and Don’ts of Applying A/D Converters”
AN042
“Interpretation of Data Conversion Accuracy
Specifications”
3
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