S25FL128SDSNFVC00 Просмотр технического описания (PDF) - Cypress Semiconductor
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S25FL128SDSNFVC00
Cypress Semiconductor
S25FL128SDSNFVC00 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
Table 10.4 CFI System Interface String
Byte Address
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
Data
27h
36h
00h
00h
06h
08h (256B page)
09h (512B page)
08h (4 kB or 64 kB)
09h (256 kB)
0Fh (128 Mb)
10h (256 Mb)
23h
02h
24h
02h
25h
03h
26h
03h
Description
VCC Min. (erase/program): 100 millivolts
VCC Max. (erase/program): 100 millivolts
VPP Min. voltage (00h = no VPP present)
VPP Max. voltage (00h = no VPP present)
Typical timeout per single byte program 2N µs
Typical timeout for Min. size Page program 2N µs
(00h = not supported)
Typical timeout per individual sector erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte program 2N times typical
Max. timeout for page program 2N times typical
Max. timeout per individual sector erase 2N times typical
Max. timeout for full chip erase 2N times typical
(00h = not supported)
Table 10.5 Device Geometry Definition for 128-Mbit and 256-Mbit Bottom Boot Initial Delivery State
Byte Address
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h thru 3Fh
Data
18h (128 Mb)
19h (256 Mb)
02h
01h
08h
00h
02h
1Fh
00h
10h
00h
FDh
00h (128 Mb)
01h (256 Mb)
00h
01h
FFh
Description
Device Size = 2N bytes
Flash Device Interface Description:
0000h = x8 only
0001h = x16 only
0002h = x8/x16 capable
0003h = x32 only
0004h = Single I/O SPI, 3-byte address
0005h = Multi I/O SPI, 3-byte address
0102h = Multi I/O SPI, 3- or 4-byte address
Max. number of bytes in multi-byte write = 2N
(0000 = not supported
0008h = 256B page
0009h = 512B page)
Number of Erase Block Regions within device
1 = Uniform Device, 2 = Boot Device
Erase Block Region 1 Information (refer to JEDEC JEP137):
32 sectors = 32-1 = 001Fh
4-kB sectors = 256 bytes x 0010h
Erase Block Region 2 Information:
254 sectors = 254-1 = 00FDh (128 Mb)
510 sectors = 510-1 = 01FDh (256 Mb)
64-kB sectors = 0100h x 256 bytes
RFU
Note:
1. FL-S 128 Mbit and 256-Mbit devices have either a hybrid sector architecture with thirty two 4-kB sectors and all remaining sectors of 64-kB or with uniform 256-kB
sectors. Devices with the hybrid sector architecture are initially shipped from Cypress with the 4 kB sectors located at the bottom of the array address map. However,
the device configuration TBPARM bit CR1[2] may be programed to invert the sector map to place the 4-kB sectors at the top of the array address map. The CFI
geometry information of the above table is relevant only to the initial delivery state of a hybrid sector device. The flash device driver software must examine the
TBPARM bit to determine if the sector map was inverted at a later time.
Document Number: 001-98283 Rev. *I
Page 121 of 144
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