WM8721L(2004) Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM8721L Datasheet PDF : 37 Pages
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WM8721 / WM8721L
Production Data
REGISTER
ADDRESS
0000111
Digital Audio
Interface
Format
BIT
1:0
LABEL
DEFAULT
FORMAT[1:0] 10
3:2
IWL[1:0]
10
4
LRP
0
5
LRSWAP
0
6
MS
0
7
BCLKINV
0
Table 7 Digital Audio Interface Control
DESCRIPTION
Audio Data Format Select
11 = DSP Mode, frame sync +
2 data packed words
10 = I2S Format, MSB-First
left-1 justified
01 = MSB-First, left justified
00 = MSB-First, right justified
Input Audio Data Bit Length
Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
DACLRC phase control (in left,
right or I2S modes)
1 = Right Channel DAC data
when DACLRC high
0 = Right Channel DAC data
when DACLRC low
(opposite phasing in I2S mode)
or
DSP mode A/B select ( in DSP
mode only)
1 = MSB is available on 2nd
BCLK rising edge after
DACLRC rising edge
0 = MSB is available on 1st
BCLK rising edge after
DACLRC rising edge
DAC Left Right Clock Swap
1 = Right Channel DAC Data
Left
0 = Right Channel DAC Data
Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
1 = Invert BCLK
0 = Don’t invert BCLK
Note: If right justified 32 bit mode is selected then the WM8721 defaults to 24 bits.
MASTER AND SLAVE MODE OPERATION
The WM8721 can be configured as either a master or slave mode device. As a master mode device
the WM8721 controls sequencing of the data and clocks on the digital audio interface. As a slave
device the WM8721 responds with data to the clocks it receives over the digital audio interface. The
mode is set with the MS bit of the control register as shown in Table 8.
REGISTER
ADDRESS
0000111
Digital Audio Interface
Format
BIT
6
LABEL
MS
Table 8 Programming Master/Slave Modes
DEFAULT
0
DESCRIPTION
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
w
PD Rev 4.0 November 2004
20
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