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9FGV0231

2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

Integrated Device Technology 

9FGV0231

2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs

TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

Slew rate

Slew rate matching

SYMBOL

Trf

ΔTrf

CONDITIONS

Scope averaging on 3.0V/ns setting

Scope averaging on 2.0V/ns setting

Slew rate matching, Scope averaging on

MIN TYP MAX UNITS NOTES

2

3

4 V/ns 1, 2, 3

1

2

3 V/ns 1, 2, 3

5

20

% 1,2,4

Voltage High

Voltage Low

VHIGH

VLOW

Statistical measurement on single-ended signal 660 793 850

1,8

using oscilloscope math function. (Scope

mV

averaging on)

-150 16 150

1

Max Voltage

Min Voltage

Vmax

Vmin

Measurement on single ended signal using

absolute value. (Scope averaging off)

-300

831

-95

1150 mV

1

1

Vswing

Vswing

Scope averaging off

300 1555

mV 1,2

Crossing Voltage (abs) Vcross_abs

Scope averaging off

300 429 550 mV 1,5

Crossing Voltage (var)

Δ-Vcross

Scope averaging off

60 140 mV 1,6

1Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 33Ω for Zo = 50Ω (100Ω differential

trace impedance).

2 Measured from differential waveform

3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on

the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross

absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.

7 At default SMBus settings.

Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common

Clocked (CC) Architectures

TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX Specification UNITS NOTES

Limit

tjphPCIeG1-CC

PCIe Gen 1

21

25

35

PCIe Gen 2 Low Band

10kHz < f < 1.5MHz

0.9

0.9

1.1

tjphPCIeG2-CC

(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)

Phase Jitter,

PCIe Gen 2 High Band

PLL Mode

1.5MHz < f < Nyquist (50MHz)

1.5

1.6

1.9

(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)

86

ps (p-p) 1, 2, 3

ps

3

(rms) 1, 2

ps

3.1

(rms) 1, 2

tjphPCIeG3-CC

PCIe Gen 3

0.3

0.37

0.44

(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)

1

ps

1, 2

(rms)

tjphPCIeG4-CC

PCIe Gen 4

(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)

0.3

0.37

0.44

ps

0.5

(rms) 1, 2

Notes on PCIe Filtered Phase Jitter Tables

1 Applies to all differential outputs, guaranteed by design and characterization.

2 Calculated from Intel-supplied Clock Jitter Tool, with spread on and off.

3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12.

IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

7

9FGV0231

JUNE 22, 2017

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