ISP1583ET Просмотр технического описания (PDF) - NXP Semiconductors.

Номер в каталоге

Компоненты Описание

производитель

ISP1583ET

Hi-Speed USB peripheral controller

NXP Semiconductors. 

NXP Semiconductors

ISP1583

Hi-Speed USB peripheral controller

8.16.1 Power-sharing mode

to GPIO of processor

for sensing VBUS

1.5 kΩ

5 V-to-3.3 V

VOLTAGE

REGULATOR

VCC(3V3)

RPU

VBUS

VBUS

USB

ISP1583

1 µF

1 MΩ

VCC(I/O)

004aaa458

VCC(I/O) is system powered.

Fig 13. Power-sharing mode

As can be seen in Figure 13, in power-sharing mode, VCC(3V3) is supplied by the output of

the 5 V-to-3.3 V voltage regulator. The input to the regulator is from VBUS. VCC(I/O) is

supplied through the power source of the system. When the USB cable is plugged in, the

ISP1583 goes through the power-on reset cycle. In this mode, OTG is disabled.

The processor will experience continuous interrupt because the default status of the

interrupt pin when operating in sharing mode with VBUS not present is LOW. To overcome

this, implement external VBUS sensing circuitry. The output from the voltage regulator can

be connected to pin GPIO of the processor to qualify the interrupt from the ISP1583.

Remark: When the core power is applied, the ISP1583 must be reset using the RESET_N

pin. The minimum width of the reset pulse width must be 2 ms.

VCC(I/O)

VCC(3V3)

INT

power off

power off

004aaa459

Fig 14. Interrupt pin status during power off in power-sharing mode

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

© NXP B.V. 2008. All rights reserved.

24 of 99

Share Link: