LTC1417IGN(RevA) Просмотр технического описания (PDF) - Linear Technology

Номер в каталоге

Компоненты Описание

производитель

LTC1417IGN
(Rev.:RevA)

Low Power 14-Bit, 400ksps Sampling ADC Converter with Serial I/O

Linear Technology 

LTC1417

TYPICAL APPLICATIONS

Listing A

***********************************************************************

*

*

* This example program retrieves data from a previous LTC1417

*

* conversion and loads the next LTC1391 MUX channel. It stores the *

* 14-bit, right justified data in two consecutive memory locations. *

* It finishes by initiating the next conversion.

*

*

*

***********************************************************************

*

************************************

* 68HC11 register definitions

*

************************************

*

PIOC EQU $1002 Parallel I/O control register

*

“STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB”

PORTC EQU $1003 Port C data register

*

“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”

DDRC EQU $1007 Port D data direction register

*

“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”

*

1 = output, 0 = input

PORTD EQU $1008 Port D data register

*

“ - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD “

DDRD EQU $1009 Port D data direction register

SPCR EQU $1028 SPI control register

*

“SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”

SPSR EQU $1029 SPI status register

*

“SPIF,WCOL, - ,MODF; - , - , - , - “

SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter

*

* RAM variables to hold the LTC1417’s 14 conversion result

*

DIN1 EQU $00 This memory location holds the LTC1417’s bits 13 - 08

DIN2 EQU $01 This memory location holds the LTC1417’s bits 07 - 00

MUX EQU $02 This memory location holds the MUX address data

*

*******************************************

* Start GETDATA Routine

*

*******************************************

*

ORG $C000 Program start location

INIT1 LDAA #$03 0,0,0,0,0,0,1,1

*

“STAF=0,STAI=0,CWOM=0,HNDS=0, OIN=0, PLS=0, EGA=1,INVB=1”

STAA PIOC Ensures that the PIOC register’s status is the same

*

as after a reset, necessary of simple Port D manipulation

LDAA #$01 0,0,0,0,0,0,0,1

*

“Bit7=input,- ,- ,- ,- ,- ,- ,Bit0=output”

*

Bit7 used for BUSY signal input, Bit0 used for CONVST

*

signal output

STAA DDRC The direction of PortD’s bits are now set

LDAA PORTC Get contents of Port C

ORAA #%00000001 Set Bit0 high

STAA PORTC Initialize CONVST to a logic high

LDAA #$2F -,-,1,0;1,1,1,1

*

-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X

STAA PORTD Keeps SS* a logic high when DDRD, bit 5 is set

LDAA #$38 -,-,1,1;1,0,0,0

STAA DDRD SS* , SCK, MOSI are configured as Outputs

*

MISO, TxD, RxD are configured as Inputs

* DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output

LDAA #$50

STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0

*

and the clock rate is E/2

24

sn1417 1417fas

Share Link: