74F322SJ Просмотр технического описания (PDF) - National ->Texas Instruments
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74F322SJ Datasheet PDF : 10 Pages
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Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
Input IIH IIL
Output IOH IOL
RE
SP
SE
S
D0 D1
CP
MR
OE
Q0
I O0 – I O7
Register Enable Input (Active LOW)
10 10
20 mA b0 6 mA
Serial (HIGH) or Parallel (LOW) Mode Control Input 1 0 1 0
20 mA b0 6 mA
Sign Extend Input (Active LOW)
10 30
20 mA b1 8 mA
Serial Data Select Input
10 20
20 mA b1 2 mA
Serial Data Inputs
10 10
20 mA b0 6 mA
Clock Pulse Input (Active Rising Edge)
10 10
20 mA b0 6 mA
Asynchronous Master Reset Input (Active LOW)
10 10
20 mA b0 6 mA
TRI-STATE Output Enable Input (Active LOW)
10 10
20 mA b0 6 mA
Bi-State Serial Output
50 33 3
b1 mA b20 mA
Multiplexed Parallel Data Inputs or
3 5 1 083
70 mA b0 65 mA
TRI-STATE Parallel Data Outputs
150 40 (33 3) b3 mA 24 mA (20 mA)
Functional Description
The ’F322 contains eight D-type edge triggered flip-flops
and the interstage gating required to perform right shift and
the intrastage gating necessary for hold and synchronous
parallel load operations A LOW signal on RE enables shift-
ing or parallel loading while a HIGH signal enables the hold
mode A HIGH signal on S P enables shift right while a
LOW signal disables the TRI-STATE output buffers and en-
ables parallel loading In the shift right mode a HIGH signal
on SE enables serial entry from either D0 or D1 as deter-
mined by the S input A LOW signal on SE enables shift right
but Q7 reloads its contents thus performing the sign extend
function required for the ’F384 Twos Complement Multiplier
A HIGH signal on OE disables the TRI-STATE output buff-
ers regardless of the other control inputs In this condition
the shifting and loading operations can still be performed
Mode Select Table
Mode
Clear
Inputs
MR RE S P SE S OE
L X X XX L
L X X XX H
Outputs
Q0
CP I O7 I O6 I O5 I O4 I O3 I O2 I O1 I O0
X
L
L
L
L
L
L
L
L
L
X
Z
Z
Z
Z
Z
Z
Z
Z
L
Parallel
Load
HL
L
X X X L I7
I6
I5
I4
I3
I2
I1
I0
I0
Shift
Right
H
L
H
HL
L L D0
O7
O6
O5
O4
O3
O2
O1 O1
H
L
H
H H L L D1
O7
O6
O5
O4
O3
O2
O1 O1
Sign
H
Extend
L
H
L X L L O7
O7
O6
O5
O4
O3
O2
O1 O1
Hold
H H X X X L L NC NC NC NC NC NC NC NC NC
When the OE input is HIGH all I On terminals are at the high impedance state sequential operation or clearing of the register is not affected
Note 1 I7–I0 e The level of the steady-state input at the respective I O terminal is loaded into the flip-flop while the flip-flop outputs (except Q0) are isolated from
the I O terminal
Note 2 D0 D1 e The level of the steady-state inputs to the serial multiplexer input
Note 3 O7–O0 e The level of the respective Qn flip-flop prior to the last Clock LOW-to-HIGH transition
H e HIGH Voltage Level
L e LOW Voltage Level
Z e High Impedance Output State
L e LOW-to-HIGH Transition
NC e No Change
3
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