QL7100-6PB516I Просмотр технического описания (PDF) - QuickLogic Corporation

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QL7100-6PB516I

Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

EclipsePlus Family Data Sheet Rev. A

Symbol

tRESET

tSW

tRW

Table 6: Logic Cells (Continued)

Parameter

Reset Delay: time between when the flip flop is ”reset” (low) and when the output is

consequently “reset” (low)

Set Width: time that the SET signal remains high/low

Reset Width: time that the RESET signal remains high/low

Value (ns)

Min. Max.

-

0.658

0.3

-

0.3

-

Figure 6: Logic Cell Flip-Flop

SET

D

Q

CLK

RESET

Figure 7: Logic Cell Flip-Flop Timings—First Waveform

CLK

SET

RESET

Q

tCWHI (min)

tCWLO (min)

tRESET

tRW

tSET

tSW

10

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