MTV112AV Просмотр технического описания (PDF) - Myson Century Inc
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MTV112AV Datasheet PDF : 20 Pages
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MYSON
TECHNOLOGY
MTV112A
(Rev 1.9)
If the control bit ENSCL is set, the block will hold SCL low until the RCBI/TXBI is cleared.
*Please see the attachments about "Slave IIC Block Timing".
Reg name addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MCTR 00h (w) LS1 LS0 LDFIFO M256 M128 ACK
P
S
MSTUS 00h (r) X SCLERR DDC2 BERR HFREQ FIFOH FIFOL BUSY
MCTR 01h (w) X
X
X
X
X
X MCLK1 MCLK0
MBUF 10h (r/w) MBUF7 MBUF6 MBUF5 MBUF4 MBUF3 MBUF2 MBUF1 MBUF0
INTFLG 50h (r/w) HPRchg VPRchg HPLchg VPLchg HFchg VFchg FIFOI MI
INTEN 60h (w) EHPR EVPR EHPL EVPL EHF EVF EFIFO EMI
FIFO 70h (w) FIFO7 FIFO6 FIFO5 FIFO4 FIFO3 FIFO2 FIFO1 FIFO0
SLVCTR 90h (w) ENSLV SLVsel ERCBI ESLVMI ETXBI ENSCL X
X
SLVSTUS 91h (r) WADR SLVS RCBI SLVMI TXBI RWB ACKIN X
SLVSTUS 91h (w)
Write to clear SLVMI
RCBUF 92h (r) RCbuf7 RCbuf6 RCbuf5 RCbuf4 RCbuf3 RCbuf2 RCbuf1 RCbuf0
TXBUF 92h (w) TXbuf7 TXbuf6 TXbuf5 TXbuf4 TXbuf3 TXbuf2 TXbuf1 TXbuf0
SLVADR 93h (w) SLVadr7 SLVadr6 SLVadr5 SLVadr4 SLVadr3 SLVadr2 SLVadr1 X
MCTR (w) : Master IIC interface control register.
LS1, LS0
= 11 → FIFOL is the status in which FIFO depth < 5.
= 10 → FIFOL is the status in which FIFO depth < 4.
= 01 → FIFOL is the status in which FIFO depth < 3.
= 00 → FIFOL is the status in which FIFO depth < 2.
LDFIFO
= 1 → FIFO will be written while S/W reads MBUF.
M256
= 1 → Disables host writing EEPROM when address is over 256.
M128
= 1 → Disables host writing EEPROM when address is over 128.
ACK
= 1 → In receiving mode, no acknowledgment is given by MTV112A.
= 0 → In receiving mode, ACK is returned by MTV112A.
S, P
= ↑, 0 → Start condition when Master IIC is not transferring.
= X, ↑ → Stop condition when Master IIC is not transferring.
= 1, X → Will resume transfer after a read/write MBUF operation.
= X, 0 → Forces HSCL low and occupies the IIC bus.
MCLK1 : MCLK0 : Master IIC speed select,
= 0 → 50KHz for 8MHz X’tal, 75KHz for 12MHz X’tal.
= 1 → 100KHz for 8MHz X’tal, 150KHz for 12MHz X’tal.
= 2 → 200KHz for 8MHz X’tal, 300KHz for 12MHz X’tal .
= 3 → 400KHz for 8MHz X’tal, 600KHz for 12MHz X’tal.
* MTV112A uses a 100KHz clock to sample the S/P bit; any pulse should sustain at least 20us.
* A write/read MBUF operation can be recognized only after 10us of the MI flag's rising edge.
MSTUS (r) : Master IIC interface status register.
SCLERR
= 1 → The ISCL pin has been pulled low by other devices during the transfer,
cleared when S=0.
DDC2
= 1 → DDC2B is active.
= 0 → MTV112A remains in DDC1 mode.
BERR
= 1 → IIC bus error, no ACK received from the slave, updated each time the
slave sends ACK on the ISDA pin.
HFREQ
= 1 → MTV112A has detected a higher than 200Hz clock on the VSYNC pin.
FIFOH
= 1 → FIFO high indicated.
FIFOL
= 1 → FIFO low indicated.
BUSY
= 1 → Host drives the HSCL pin to low.
MTV112A Revision 1.9 05/18/2001
14/20
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