MT46V16M16BG-75 Просмотр технического описания (PDF) - Micron Technology
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MT46V16M16BG-75 Datasheet PDF : 80 Pages
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256Mb: x4, x8, x16
DDR SDRAM
Figure 41: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window
T1
CK#
CK
tHP5
T2
T2n
T3
T3n
T4
tHP5
tHP5
tHP5
tDQSQ3
tDQSQ3
tHP5
tDQSQ3
tHP5
tDQSQ3
LDQS1
DQ (Last data valid)2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ (First data no longer valid)2
DQ (Last data valid)2
DQ (First data no longer valid)2
DQ0 - DQ7 and LDQS, collectively6
tQH4
T2
T2
T2
tQH4
tQH4
T2n
T3
T2n
T3
T2n
T3
tQH4
T3n
T3n
T3n
UDQS1
DQ (Last data valid)7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ (First data no longer valid)7
DQ (Last data valid)7
DQ (First data no longer valid)7
DQ8 - DQ15 and UDQS, collectively6
Data Valid Data Valid
window window
tDQSQ3
tDQSQ3
Data Valid
window
Data Valid
window
tDQSQ3
tDQSQ3
tQH4
T2
T2
T2
tQH4
T2n
tQH4
T3
tQH4
T3n
T2n
T3
T3n
T2n
T3
T3n
Data Valid Data Valid Data Valid Data Valid
window
window
window window
NOTE:
1. DQ transitioning after DQS transition define tDQSQ window. LDQS defines the lower byte and UDQS defines the upper
byte.
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with
the last valid DQ transition.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transition and is tQH minus tDQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
09005aef8076894f
256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN
66
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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