MT46V16M16BG-75ZL Просмотр технического описания (PDF) - Micron Technology
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MT46V16M16BG-75ZL Datasheet PDF : 80 Pages
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256Mb: x4, x8, x16
DDR SDRAM
Figure 26: WRITE to READ – Interrupting
CK#
CK
COMMAND
T0
WRITE
ADDRESS
Bank a,
Col b
tDQSS (NOM)
DQS
tDQSS
T1 T1n T2 T2n T3 T3n T4
NOP
NOP
READ
NOP
tWTR
Bank a,
Col n
CL = 2
T5 T5n T6 T6n
NOP
NOP
DQ
DI
b
DO
n
DM
tDQSS (MIN)
DQS
tDQSS
CL = 2
DQ
DI
b
DO
n
DM
tDQSS (MAX)
DQS
tDQSS
DQ
DI
b
DM
CL = 2
DO
n
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI b = data-in for column ;, DO n = data-out for column n.
2. An interrupted burst of 4 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 was used, DM and DQS would be required at T3 and T3n because the READ command would not mask
these two data elements.
09005aef8076894f
256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN
35
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©2003 Micron Technology, Inc.
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