UPD30550 Просмотр технического описания (PDF) - NEC => Renesas Technology

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производитель

UPD30550

VR5500™ 64-/32-BIT MICROPROCESSOR

NEC => Renesas Technology 

µPD30550

(4) Clock interface signals

Pin Name

SysClock

VDDPA1

VDDPA2

VSSPA1

VSSPA2

I/O

Input

−

−

System clock

Clock input to the processor

VDD for PLL

Power supply for the internal PLL

VSS for PLL

Ground for the internal PLL

Function

(5) Power supply

Pin Name

VDD

VDDIO

VSS

I/O

− Power supply pin for core

− Power supply pin for I/O

− Ground potential pin

Function

Caution The VR5500 uses two separate power supply pins. The power supply pins can be applied in any

sequence. Power application to the pins must occur within 100ms of each other.

(6) Test interface signals

Pin Name

NTrcData(3:0)

NTrcEnd

NTrcClk

RMode#/

BKTGIO#

JTDI

JTDO

JTMS

JTCK

JTRST#

I/O

Output

Output

Output

I/O

Input

Output

Input

Input

Input

Function

Trace data

Trace data output

Trace end

This signal indicates the end of a trace data packet.

Trace clock

Clock for the test interface. The same clock as SysClock is output.

Reset mode/break trigger I/O

When the JTRST# signal is active, this is a debug reset mode input signal .

During normal operation this serves as a break or trigger I/O signal.

JTAG data input

Serial data input for JTAG

JTAG data output

Serial data output for JTAG. Output is performed in synchronization with the rise of JTCK.

JTAG mode select

This signal selects the JTAG test mode.

JTAG clock input

Serial clock input for JTAG. The maximum frequency is 33 MHz. There is no need for it to be

synchronized with SysClock.

JTAG reset input

A signal for initializing the JTAG test module.

Data Sheet U15700EJ1V0DS

11

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