STM8AP62A8UAX Просмотр технического описания (PDF) - STMicroelectronics

Номер в каталоге

Компоненты Описание

производитель

STM8AP62A8UAX

Automotive 8-bit MCU, with up to 128 Kbyte Flash, data EEPROM, 10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 to 5.5 V

STMicroelectronics 

Revision history

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

Date

30-Jan-2011

Table 55. Document revision history (continued)

Revision

Changes

Modified references to reference manual, and Flash programming

manual in the whole document.

Added reference to AEC Q100 standard on cover page.

Renamed timer types as follows:

– Auto-reload timer to general purpose timer

– Multipurpose timer to advanced control timer

– System timer to basic timer

Introduced concept of high density Flash program memory.

Updated the number of I/Os for devices in 80-, 64-, and 48-pin

packages in Table: STM8AF52xx product line-up with CAN, Table:

STM8AF62xx product line-up without CAN, Table: STM8AF/H/P51xx

product line-up with CAN, and Table: STM8AF/H/P61xx product line-

up without CAN.

Added TMU brief description in Section 5.4: Flash program and data

EEPROM, updated TMU_MAXATT description in Table 19: Option

byte description, and TMU_MAWATT reset value in Table 18: Option

bytes.

Updated clock sources in Section 5.5.1: Features.

Added Table 4: Peripheral clock gating bits (CLK_PCKENR1).

Added calibration using TIM3 in Section 5.7.2: Auto-wakeup counter.

Added Table 8: ADC naming and Table 9: Communication peripheral

naming correspondence.

8

Updated SPI data rate to fMASTER/2 in Section 5.9.3: Serial

peripheral interface (SPI).

Added reset state in Table 10: Legend/abbreviation for the pin

description table.

Table: STM8A microcontroller family pin description: modified

footnotes related to PD1/SWIM, corrected wpu input for PE1 and

PE2, and renamed TIMn_CCx and TIMn_NCCx to TIMn_CHx and

TIMn_CHxN, respectively.

Section: Register map: Removed CAN register CLK_CANCCR.

Removed I2C_PECR register.

Added footnote for Px_IDR registers in Table 13: I/O port hardware

register map. Updated register reset values for Px_IDR and PD_CR1

registers.

Replaced tables describing register maps and reset values for non-

volatile memory, global configuration, reset status, TMU, clock

controller, interrupt controller, timers, communication interfaces, and

ADC, by TTable 14: General hardware register map. Added debug

module register map

Renamed Fast Active Halt mode to Active-halt mode with regulator

on, and Slow Active Halt mode to Active-halt mode with regulator off,

updated Section 5.6: Low-power operating modes, and Table 27:

Total current consumption in Halt and Active-halt modes. General

conditions for VDD applied. TA = -40 °C to 55 °C unless otherwise

stated. IDD(FAH) and IDD(SAH) renamed IDD(AH); tWU(FAH) and tWU(SAH)

renamed tWU(AH).

120/125

DocID14395 Rev 15

Share Link: