74AHC08BQ-Q100 Просмотр технического описания (PDF) - NXP Semiconductors.

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производитель

74AHC08BQ-Q100

Quad 2-input AND gate

NXP Semiconductors. 

Nexperia

4. Functional diagram

74AHC08-Q100; 74AHCT08-Q100

Quad 2-input AND gate

1 1A

2 1B

4 2A

5 2B

9 3A

10 3B

12 4A

13 4B

1Y 3

2Y 6

3Y 8

4Y 11

mna222

Fig 1. Logic symbol

1

&

3

2

4

&

6

5

9

&

8

10

12

&

11

13

mna223

Fig 2. IEC logic symbol

5. Pinning information

5.1 Pinning

A

Y

B

mna221

Fig 3. Logic diagram (one gate)

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*1' 

 9&&

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 $

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DDD

Fig 4. Pin configuration SO14 and TSSOP14

WHUPLQDO 

LQGH[ DUHD

$+&4

$+&74

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DDD

7UDQVSDUHQW WRS YLHZ

(1) The die substrate is attached to this pad using

conductive die attach material. It cannot be used as a

supply pin or input.

Fig 5. Pin configuration DHVQFN14

74AHC_AHCT08_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 16 April 2013

© Nexperia B.V. 2017. All rights reserved

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