ACT8897
Rev 2, 05-Sep-13
SYSTEM CONTROL INFORMATION
Interfacing with the Samsung S5PC100, S5PC110 and S5PV210 Processors
The ACT8897 is optimized for use in applications
using the S5PC100, S5PC110 and S5PV210
processors, supporting both the power domains as
well as the signal interface for these processors.
The following paragraphs describe how to design
ACT8897 with S5PV210 Processor, but the design
guidelines are directly applicable to S5PC100 and
S5PC110 as well.
While the ACT8897 supports many possible
configurations for powering these processors, one
of the most common configurations is detailed in
this datasheet. In general, this document refers to
the ACT8897 pin names and functions. However, in
cases where the description of interconnections
between these devices benefits by doing so, both
the ACT8897 pin names and the Samsung
processor pin names are provided. When this is
done, the S5PV210 pin names are located after the
ACT8897 pin names, and are italicized and located
inside parentheses. For example, PWREN
(XPWRRGTON) refers to the logic signal applied to
the ACT8897's PWREN input, identifying that it is
driven from the S5PV210's XPWRRGTON output.
Likewise, OUT1 (VDD_IO) refers to ACT8897's
OUT1 pin, identifying that it is connected to the
S5PV210's VDD_IO power domain.
Table 2:
ACT8897 and Samsung S5PV210 Power Domains
POWER DOMAIN
VDD_IO
VDD_INT
VDD_ARM
VDD_xPLL
VDD_Alive
VDD_UOTG_D
VDD_UOTG_A
ACT8897 CHANNEL
REG1
REG2
REG3
REG4
REG5
REG6
REG7
TYPE
DC/DC
DC/DC
DC/DC
LDO
LDO
LDO
LDO
DEFAULT VOLTAGE
3.3V
1.1V
1.25V/1.25V
1.1V
1.1V
1.1V
3.3V
CURRENT CAPABILITY
1100mA
1100mA
1200mA
150mA
150mA
250mA
250mA
Table 3:
ACT8897 and Samsung S5PV210 Power Modes
POWER
MODE
ALL ON
NORMAL
SLEEP
ALL OFF
CONTROL STATE
POWER DOMAIN STATE
QUIESCENT
CURRENT
PWRHLD is asserted, PWREN is asserted
REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 are all on
420µA
PWRHLD is asserted, PWREN is asserted,
REG6 and REG7 are disabled after system
boots up.
REG1, REG2, REG3, REG4 and
REG5 are on. REG6 and REG7 are off
340µA
PWRHLD is asserted, PWREN is de-asserted, REG1 and REG5 are on. REG2, REG3,
REG6 and REG7 are disabled default.
REG4, REG6 and REG7 are off
190µA
PWRHLD is de-asserted, PWREN is
de-asserted
REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 are all off
<18µA
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