SMJ4C1024JD Просмотр технического описания (PDF) - Austin Semiconductor

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SMJ4C1024JD

1048576 by 1-bit dynamic random-access memory

Austin Semiconductor 

SMJ4C1024

1048576 BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SGMS023E – DECEMBER 1988 – REVISED MARCH 1996

A0 – A9

CAS

D

NC

Q

RAS

TF

VCC

VSS

W

PIN NOMENCLATURE

Address Inputs

Column Address Strobe

Data In

No Internal Connection

Data Out

Row Address Strobe

Test Function

5-V Supply

Ground

Write Enable

description

The SMJ4C1024 is a 1 048 576-bit DRAM organized as 1 048 576 words of one bit each. It employs technology

for high performance, reliability, and low power at a low cost.

This device features maximum RAS access times of 80 ns, 100 ns, 120 ns, and 150 ns. Maximum power

dissipation is as low as 305 mW operating and 16.5 mW standby on 150-ns devices.

IDD peaks are typIcally 140 mA and a –1 V input voltage undershoot can be tolerated, minimizing system noise.

All inputs and outputs, including clocks, are compatible with series 54 TTL. All addresses and data-in lines are

latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.

The SMJ4C1024 is offered in an 18-pin ceramic dual-in-line package (JD suffix), a 20 / 26-terminal leadless

ceramic carrier package (FQ / HL suffixes), a 20 / 26-pin J-leaded carrier package (HJ suffix), a 20-pin flatpack

(HK suffix), and a 20-pin ceramic zig-zag in-line package (SV suffix). They are characterized for operation from

– 55°C to 125°C.

2

• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

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