MB90091A Просмотр технического описания (PDF) - Fujitsu

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MB90091A

Intelligent on-screen display controller (IOSDC)

Fujitsu 

MB90091A

The MB90091A outputs display signals in synchronization with sync signals input from external circuits. The

signals required for controlling synchronization are the horizontal sync signal (input via the HSYNC pin), vertical

sync signal (input via the VSYNC pin), and field control signal (input via the EVEN pin).

The following examples illustrate external sync signal input timings applicable to general interlaced display.

Noninterlaced display does not require the EVEN pin signal.

• External sync signal input timing examples

(1) Field A

VSYNC

FH

(HSYNC) *1

EVEN

Slow *2

*2

(2) Field B

VSYNC

FH

(HSYNC) *1

EVEN

Fast *2

*2

*1: Input the horizontal sync signal to the HSYNC pin.

Input of a composite sync signal may change the FH signal cycle due to the PLL lock disturbed around

the VSYNC pulse, requiring a caution to be used for the timing of input to the EVEN pin. (See *2 below.)

*2: The input levels of the EVEN pin input signal in fields A and B are determined depending on the

relationship between the VSYNC and FH pulse positions. To the EVEN pin, input the “L” level signal in

the field in which the FH pulse after the rise of the VSYNC pulse appears fast. Pin the “H” level signal

in the field in which it appears slow.

The EVEN pin input signal should vary in the undisplay period such as around the VSYNC pulse.

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