E-STE10/100A Просмотр технического описания (PDF) - STMicroelectronics

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E-STE10/100A

PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STMicroelectronics 

Overview

1

Overview

STE10/100A

1.1

Block diagrams

Figure 1. STE10/100A block diagram

Flow

control

DMA

Tx FiFo

Rx FiFo

EMI

Manchester

encoder

10 TX filter

4B/5B

Scrambler

Auto-negociation

5B/4B

Descrambler

100 clock

recovery

Manchester

decoder

Transmitter

25MHz

Base line

restore

125MHz

TX freq. synth.

20MHz

Adaptive

equalization

Link polarity

10 clock

recovery

PC00347

Figure 2. STE10/100A system diagram

Serial EEPROM

Boot ROM

PCI

interface

STE10/100A

Xfmr

Medium

LEDs

25MHz crystal

PC00348

4/82

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