MAX7358 Просмотр технического описания (PDF) - Maxim Integrated
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MAX7358
Maxim Integrated
MAX7358 Datasheet PDF : 22 Pages
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1-to-8 I2C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
ELECTRICAL CHARACTERISTICS (5V SUPPLY) (continued)
(VDD = +4.5V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +5V, TA = +25°C.) (Notes 2–5)
PARAMETER
Input Capacitance
PASS GATE
Switch Resistance
Switch Output Voltage
Leakage Current
Input/Output Capacitance
OUTPUT RST/INT
Low-Level Output Current
Leakage Current
SYMBOL
CI
VI = GND
CONDITIONS
MIN TYP MAX UNITS
2
pF
RON VDD = 4.5V to 5.5V, VO = 0.4V, IO = 15mA
4
9
24
Ω
VSW
VSWin = VDD = 5.0V, ISWout = -100µA
VSWin = VDD = 4.5V to 5.5V, ISWout = -100µA
2.6
3.6
4.5
V
MAX7356
-1
+1
IL
VI = VDD or GND
Enhanced mode
(MAX7357/MAX7358)
-2
µA
+2
CIO
VI = GND
3
pF
IOL
VOL = 0.4V (MAX7357/MAX7358)
3
ILH, ILI VRST/INT = VDD or GND
-1
mA
+1
µA
TIMING CHARACTERISTICS (STANDARD-MODE) (Figures 1, 2, 3)
(VDD = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
Propagation Delay from SDA to
SD_ or SCL to SC_
tPD
(Note 7)
SCL Clock Frequency
fSCL
0
Bus Free Time Between a STOP
and START Condition
tBUF
4.7
Hold Time (Repeated) START
Condition After this Period, the
tHD;STA
4.0
First Clock Pulse is Generated
LOW Period of the SCL Clock
tLOW
4.7
HIGH Period of the SCL Clock
tHIGH
4.0
Setup Time for a Repeated
START Condition
tSU;STA
4.7
Setup Time for a STOP Condition tSU;STO
4.0
Data Hold Time
tHD;DAT (Note 8)
0
Data Setup Time
tSU;DAT
250
Rise Time of Both SDA and SCL
Signals
tR
Fall Time of Both SDA and SCL
Signals
tF
Capacitive Load for Each Bus
Line
Cb
Pulse Width of Spikes that Must
be Suppressed by the Input Filter
tSP
TYP MAX UNITS
0.3
ns
100
kHz
µs
µs
µs
µs
µs
µs
3.45
µs
ns
1000
ns
300
ns
400
pF
50
ns
4 _______________________________________________________________________________________
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