MAX1460 Просмотр технического описания (PDF) - Maxim Integrated

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MAX1460

Low-Power, 16-Bit Smart ADC

Maxim Integrated 

MAX1460

Low-Power, 16-Bit Smart ADC

(16 n + 9)th CLOCK CYCLE

(16 (n + 1) + 9)th CLOCK CYCLE

XIN

LSB

MSB

SDO S12 S13 S14 S15 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11

LSB

MSB LSB

MSB

SDIO PS4 PS5 PS6 PS7 P0 P1 P2 P3 P4 P5 P6 P7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 P0 P1 P2 P3 P4 P5 P6 P7 PS0 PS1 PS2 PS3

DSP CYCLE n-1

DSP CYCLE n

DSP CYCLE n+1

NOTE: ALL TRANSITIONS MUST OCCUR WITHIN 100ns OF THE XIN CLOCK EDGE.

Figure 4. DSP Serial Output Timing Diagram

VDD

START

(OPTIONAL)

SDIO & SDO

(TEST MODE)

D [11...0]

tWARM

tCONV

tADC

tDSP

EOC

tEOC

Figure 5. MAX1460 Conversion Timing

XIN clock signal. When the P and PS registers in Table 8

appear on SDIO, the tester should save the correspond-

ing SDO data.

The conversion timing of the MAX1460 is shown in Figure

5 and Table 9. In the figure, the conversion is initiated by

a rising transition on the START pin. Equivalently, conver-

sion can be initiated in TEST mode after completion of

tester commands 8 hex or A hex, or reinitiated by the state

of the Repeat Mode bit in the configuration register. After

a conversion is initiated, the 16-bit ADC digitizes the tem-

perature and sensor signals during tADC. Then, the DSP

executes the instruction ROM microcode during tDSP. In

TEST mode, and during tDSP, SDIO and SDO outputs

carry useful information. At 130,586 clock cycles after the

Start Conversion command is received, the LSB of the S

and P DSP registers is available on SDO and SDIO. The

last DSP instruction is D0 hex. The tester can now start a

new communication sequence by lowering the RESET pin

for at least 16 clock cycles, and then resume driving SDIO.

SDIO becomes high impedance when RESET is low.

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