ISPLSI3256E-100LQ Просмотр технического описания (PDF) - Lattice Semiconductor

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производитель

ISPLSI3256E-100LQ

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 3256E

ispLSI 3256E Timing Model

I/O Cell

GRP

I/O Pin

(Input)

#52

I/O Reg Bypass

#24

Input

D Register Q

RST

#25 - 29

Reset

Y3,4

#51

GRP

#30

#50

Y0,1,2

GOE0,1

#53

TOE

#54

GLB

Feedback

4 PT Bypass

#32

20 PT

XOR Delays

#33 - 35

#52

#31

GLB Reg Bypass

#36

GLB Reg

Delay

D

Q

RST

#37 - 40

ORP

I/O Cell

ORP Bypass

#45

ORP

Delay

#44

#46, 47

I/O Pin

(Output)

#48, 49

Control RE

PTs OE

#41 - 43 CK

0902/3256E

Derivations of tsu, th and tco from the Product Term Clock1

tsu

= Logic + Reg su - Clock (min)

= (tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min))

= (#24+ #30+ #34) + (#37) - (#24+ #30+ #43)

1.4 ns = (2.4 + 2.3 + 4.1) + (0.3) - (2.4 + 2.3 + 3.0)

th

= Clock (max) + Reg h - Logic

= (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor)

= (#24+ #30+ #43) + (#38) - (#24+ #30+ #34)

4.5 ns = (2.4 + 2.3 + 3.6) + (5.0) - (2.4 + 2.3 + 4.1)

tco

= Clock (max) + Reg co + Output

= (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob)

= (#24 + #30 + #43) + (#39) + (#44 + #46)

13.7 ns = (2.4 + 2.3 + 3.6) + (1.6) + (1.2 + 2.6)

Table 2- 0042-3256E

Note: Calculations are based upon timing specifications for the ispLSI 3256E-100L.

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