PH9030L Просмотр технического описания (PDF) - NXP Semiconductors.
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PH9030L Datasheet PDF : 12 Pages
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NXP Semiconductors
PH9030L
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pinning information
Pin
Symbol Description
1,2,3 S
source
4
G
gate
mb
D
mounting base; connected to
drain
3. Ordering information
Simplified outline
mb
1234
SOT669
(LFPAK)
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
PH9030L
LFPAK
4. Limiting values
Description
Version
Plastic single-ended surface-mounted package (LFPAK); SOT669
4 leads
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDS
VDGR
VGS
ID
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
25 °C ≤ Tj ≤ 150 °C
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
VGS = 10 V; Tj = 100 °C; see Figure 1
VGS = 10 V; Tmb = 25 °C; see Figure 1;
see Figure 3
IDM
peak drain current
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see
Figure 3
Ptot
total power dissipation
Tstg
storage temperature
Tj
junction temperature
Source-drain diode
Tmb = 25 °C; see Figure 2
IS
source current
ISM
peak source current
Avalanche Ruggedness
Tmb = 25 °C
tp ≤ 10 µs; pulsed; Tmb = 25 °C
EDS(AL)S
non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 33 A;
Vsup ≤ 30 V; unclamped; tp = 0.08 ms;
RGS = 50 Ω
Min Max Unit
-
30
V
-
30
V
-20 20
V
-
39
A
-
63
A
-
214 A
-
62.5 W
-55 150 °C
-55 150 °C
-
52
A
-
208 A
-
53
mJ
PH9030L_1
Product data sheet
Rev. 01 — 29 July 2008
© NXP B.V. 2008. All rights reserved.
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