PCA9543BPW,118(2014) Просмотр технического описания (PDF) - NXP Semiconductors.
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PCA9543BPW,118 Datasheet PDF : 28 Pages
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NXP Semiconductors
PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
7.5 Bus transactions
Data is transmitted to the PCA9543A/43B control register using the Write mode as shown
in Figure 12.
slave address
control register
SDA S 1 1 1 0 0 A1 A0 0 A X X X X X X B1 B0 A P
START condition
R/W acknowledge
from slave
acknowledge
from slave
STOP condition
002aab182
Fig 12. Write control register
Data is read from PCA9543A/43B using the Read mode as shown in Figure 13.
slave address
control register
last byte
SDA S 1 1 1 0 0 A1 A0 1 A X X INT1 INT0 X X B1 B0 NA P
START condition
Fig 13. Read control register
R/W acknowledge
from slave
no acknowledge
from master
STOP condition
002aab183
PCA9543A_43B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 3 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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