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MPC9230FN

800MHz Low Voltage PECL Clock Synthesizer

Integrated Device Technology 

MPC9230 Data Sheet

800MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER

Table 1. Pin Configurations

Pin

I/O

XTAL_IN, XTAL_OUT

FREF_EXT

Input

FOUT, FOUT

TEST

Output

Output

XTAL_SEL

Input

S_LOAD

Input

Default

0

1

0

P_LOAD

Input

1

S_DATA

S_CLOCK

M[0:8]

N[1:0]

OE

GND

VCC

VCC_PLL

Input

0

Input

0

Input

1

Input

1

Input

1

Supply

Supply

Supply

Type

Analog

LVCMOS

LVPECL

LVPECL

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

Ground

VCC

VCC

Function

Crystal oscillator interface

Alternative PLL reference input

Differential clock output

Test and device diagnosis output

PLL reference select input

Serial configuration control input

This input controls the loading of the configuration latches with the contents of the shift register.

The latches will be transparent when this signal is high, thus the data must be stable on the

high-to-low transition.

Parallel configuration control input.

This input controls the loading of the configuration latches with the content of the parallel inputs

(M and N). The latches will be transparent when this signal is low, thus the parallel data must

be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive.

Serial configuration data input

Serial configuration clock input

Parallel configuration for PLL feedback divider (M).

M is sampled on the low-to-high transition of P_LOAD

Parallel configuration for Post-PLL divider (N).

N is sampled on the low-to-high transition of P_LOAD

Output enable (active high)

The output enable is synchronous to the output clock to eliminate the possibility of runt pulses

on the FOUT output

Negative power supply (GND)

Positive power supply for I/O and core. All VCC pins must be connected to the positive power

supply for correct operation

PLL positive power supply (analog power supply)

Table 2. Output Frequency Range and PLL Post-Divider N

N

1

0

Output Division

Output Frequency Range

for TA = 0°C to +70°C

0

0

2

200 – 400 MHz

0

1

4

100 – 200 MHz

1

0

8

50 – 100 MHz

1

1

1

400 – 800 MHz

Output Frequency Range

for TA = –40°C to +85°C

200 – 375 MHz

100 – 187.5 MHz

50 – 93.75 MHz

400 – 750 MHz

Table 3. Function Table

Input

XTAL_SEL

OE

0

FREF_EXT

Outputs disabled. FOUT is stopped in the logic low state

(FOUT = L, FOUT = H)

1

XTAL interface

Outputs enabled

MPC9230 REVISION 8 MARCH 29, 2010

3

©2010 Integrated Device Technology, Inc.

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