Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 31)
VIH
/RAS
VIL
VIH
/CAS
VIL
VIH
Address
VIL
VIH
/W
VIL
tRC
tRAS
tCRP
tRCD
tRSH
tASR
tRAD
tRAH tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tRCS
tRAL
tDZC
DQ
VIH
(INPUTS)
VIL
DQ
(OUTPUTS)
VOH
VOL
VIH
/OE
VIL
tCAC
tAA
tCLZ
Hi-Z
tRAC
tDZO
tOEA
tORH
tRC
tRP
tRAS
tRP
tCHR
tASR
ROW
ADDRESS
tRRH
tRCH
Hi-Z
DATA VALID
tCDD
tRDD
tREZ
tOHR
tOFF
tOHC
Hi-Z
tOEZ
tODD
Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
MIT-DS-0241-0.0
MITSUBISHI
ELECTRIC
( 21 / 22 )
28/Jul/`98