MCP2030 Просмотр технического описания (PDF) - Microchip Technology
Номер в каталоге
Компоненты Описание
производитель
MCP2030 Datasheet PDF : 66 Pages
| |||
MCP2030
AC Characteristics
Electrical Specifications: Standard Operating Conditions (unless otherwise stated)
Supply Voltage
Operating temperature
LCCOM connected to VSS
LC Signal Input
Carrier Frequency
2.0V ≤ VDD ≤ 3.6V
-40°C ≤ TA ≤ +85°C
Sinusoidal 300 mVPP
125 kHz
LCCOM connected to VSS
Parameters
Sym.
Min.
Typ†
Max.
Input Sensitivity
VSENSE
1
3.0
6
Coil de-Q’ing Voltage -
RF Limiter (RFLM) must be active
RF Limiter Turn-on Resistance
(LCX, LCY, LCZ)
Sensitivity Reduction
Minimum Modulation Depth
60% setting
33% setting
14% setting
8%
Carrier frequency
Input modulation frequency
VDE_Q
3
—
5
RFLM
—
300
700
SADJ
—
0
—
—
-30
—
VIN_MOD
—
60
84
—
33
49
—
14
26
8
FCARRIER
—
125
—
FMOD
—
—
10
LCX Tuning Capacitor
CTUNX
—
0
—
Units
mVPP
V
Conditions
VDD = 3.0V
Output enable filter disabled
AGCSIG = 0; MODMIN = 00
(33% modulation depth setting)
Input = Continuous Wave (CW)
Output = Logic level transition from
low-to-high at sensitivity level for CW input.
VDD = 3.0V, Force IIN = 5 μA (worst case)
Ω
VDD = 2.0V, VIN = 8 VDC
VDD = 3.0V
dB No sensitivity reduction selected
dB Max. reduction selected
Monotonic increment in attenuation value
from setting = 0000 to 1111 by design
VDD = 3.0V
% See Section 5.21 “Minimum Modulation
% Depth Requirement for Input Signal”.
% See Modulation Depth Definition in
% Figure 5-5.
kHz
kHz Input data rate with NRZ data format.
VDD = 3.0V
Minimum modulation depth setting = 33%
Input conditions:
Amplitude = 300 mVPP
Modulation depth = 100%
VDD = 3.0V,
pF Config. Reg. 1, bits <6:1> Setting = 000000
LCY Tuning Capacitor
44
59
82
CTUNY
—
0
—
pF 63 pF ±30%
Config. Reg. 1, bits <6:1> Setting = 111111
63 steps, approx. 1 pF/step
Monotonic increment in capacitor value from
setting = 000000 to 111111 by design
VDD = 3.0V,
pF Config. Reg. 2, bits <6:1> Setting = 000000
LCZ Tuning Capacitor
44
59
82
CTUNZ
—
0
—
pF 63 pF ±30%
Config. Reg. 2, bits <6:1> Setting = 111111
63 steps, approx. 1 pF/step
Monotonic increment in capacitor value from
setting = 000000 to 111111 by design
VDD = 3.0V,
pF Config. Reg. 3, bits<6:1> Setting = 000000
44
59
82
pF 63 pF ±30%
Config. Reg. 3, bits<6:1> Setting = 111111
63 steps, approx. 1 pF/step
Monotonic increment in capacitor value from
setting = 000000 to 111111 by design
Q of Internal Tuning Capacitors
Q_C
50 *
—
—
Demodulator Charge Time
TDR
—
50
—
(delay time of demodulated output to rise)
μs VDD = 3.0V
Minimum modulation depth setting = 33%
Input conditions:
Amplitude = 300 mVPP
Modulation depth = 100%
* Parameter is characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF).
2: Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).
DS21981A-page 4
© 2005 Microchip Technology Inc.
Share Link: 