M66282FP Просмотр технического описания (PDF) - Renesas Electronics

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M66282FP

8192 × 8-Bit Line Memory

Renesas Electronics 

M66282FP

Reading Shortest n-cycle Write Data "n"

(Reading side n − 1 cycle starts after the end of writing side n − 1 cycle)

When the reading side n − 1 cycle starts before the end of the writing side n + l cycle, output Qn of n cycle is made

invalid. In the following diagram, reading operation of n − 1 cycle is invalid.

WCK

Dn

RCK

Qn

n cycle

n + 1 cycle

n + 2 cycle

n + 3 cycle

(n)

(n +1)

(n +2)

n − 2 cycle

n − 1 cycle

(n +3)

n cycle

Invalid

(n)

Reading Longest n-cycle Write Data "n": 1 Line Delay

(When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts)

Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle

<2>* overlap each other.

WCK

n cycle <1>*

0 cycle <2>*

n cycle <2>*

Dn

RCK

(n − 1) <1>*

(n) <1>*

n cycle <0>*

(0) <2>*

0 cycle <1>*

(n − 1) <2>*

(n) <2>*

n cycle <1>*

Qn

(n − 1) <0>*

(n) <0>*

Note: <0>*, <1>* and <2>* indicate value of lines.

(0) <1>*

(n − 1) <1>*

(n) <1>*

REJ03F0255-0200 Rev.2.00 Sep 14, 2007

Page 11 of 13

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