L7400 Просмотр технического описания (PDF) - Intel

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L7400

Intel® Core™2 Duo Mobile Processor for Intel® Centrino® Duo Mobile Processor Technology

Intel 

Low Power Features

2.5

The processor incorporates the DPWR# signal that controls the data bus input buffers

on the processor. The DPWR# signal disables the buffers when not used and activates

them only when data bus activity occurs, resulting in significant power savings with no

performance impact. BPRI# control also allows the processor address and control input

buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows

a reciprocal power reduction in chipset address and control input buffers when the

processor deasserts its BR0# pin. The On-die Termination on the processor FSB buffers

is disabled when the signals are driven low, resulting in additional power savings. The

low I/O termination voltage is on a dedicated voltage plane independent of the core

voltage, enabling low I/O switching power at all times.

Processor Power Status Indicator (PSI#) Signal

The processor incorporates the PSI# signal that is asserted when the processor is in a

reduced power consumption state. PSI# can be used to improve intermediate and light

load efficiency of the voltage regulator, resulting in platform power savings and

extended battery life. The algorithm that the processor uses for determining when to

assert PSI# is different from the algorithm used in previous Intel® Pentium® M

processors. For Intel Core 2 processor with Intel Centrino Duo mobile technology, PSI#

signal functionality is supported only in idle state.

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Datasheet

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