ADT7411ARQZ10 Просмотр технического описания (PDF) - Analog Devices
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ADT7411ARQZ10
Analog Devices
ADT7411ARQZ10 Datasheet PDF : 36 Pages
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ADT7411
Table 7. ADT7411 Registers
RD/WR
Address Name
00h
Interrupt Status 1
01h
Interrupt Status 2
02h
Reserved
03h
Internal Temp and VDD LSBs
04h
External Temp and AIN1–4 LSBs
05h
AIN5–8 LSBs
06h
VDD MSBs
07h
Internal Temperature MSBs
08h
External Temp MSBs/AIN1 MSBs
09h
AIN2 MSBs
0Ah
AIN3 MSBs
0Bh
AIN4 MSBs
0Ch
AIN5 MSBs
0Dh
AIN6 MSBs
0Eh
AIN7 MSBs
0Fh
AIN8 MSBs
10h–17h Reserved
18h
Control CONFIG 1
19h
Control CONFIG 2
1Ah
Control CONFIG 3
1Bh–1Ch Reserved
1Dh
Interrupt Mask 1
1Eh
Interrupt Mask 2
1Fh
Internal Temp Offset
20h
External Temp Offset
21h
Reserved
22h
Reserved
23h
VDD VHIGH Limit
24h
VDD VLOW Limit
25h
Internal THIGH Limit
26h
Internal TLOW Limit
27h
External THIGH/AIN1 VHIGH Limits
28h
External TLOW/AIN1 VLOW Limits
29h–2Ah Reserved
2Bh
AIN2 VHIGH Limit
2Ch
AIN2 VLOW Limit
2Dh
AIN3 VHIGH Limit
2Eh
AIN3 VLOW Limit
2Fh
AIN4 VHIGH Limit
30h
AIN4 VLOW Limit
31h
AIN5 VHIGH Limit
32h
AIN5 VLOW Limit
33h
AIN6 VHIGH Limit
34h
AIN6 VLOW Limit
35h
AIN7 VHIGH Limit
36h
AIN7 VLOW Limit
37h
AIN8 VHIGH Limit
38h
39h–4Ch
AIN8 VLOW Limit
Reserved
4Dh
Device ID
4Eh
Manufacturer’s ID
4Fh
Silicon Revision
50h–7Eh Reserved
7F
SPI Lock Status
80h–FFh Reserved
Power-On
Default
00h
00h
00h
00h
00h
xxh
00h
00h
00h
00h
00h
00h
00h
00h
00h
08h
00h
00h
00h
00h
00h
00h
C7h
62h
64h
C9h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
02h
41h
04h
00h
00h
00h
Interrupt Status 1 Register (Read-Only) [Address = 00h]
This 8-bit read-only register reflects the status of some of the
interrupts that can cause the INT/INT pin to go active. This
register is reset by a read operation, provided that any out-of-
limit event has been corrected. It is also reset by a software reset.
Table 8. Interrupt Status 1 Register
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
Table 9.
Bit Function
D0 1 when internal temperature value exceeds THIGH limit. Any
internal temperature reading greater than the set limit will
cause an out-of-limit event.
D1 1 when internal temperature value exceeds TLOW limit. Any
internal temperature reading less than or equal to the set
limit will cause an out-of-limit event.
D2 This status bit is linked to the configuration of pins 7 and 8.
If configured for external temperature sensor, this bit is 1
when external temperature value exceeds THIGH limit. The
default value for this limit register is –1°C, so any external
temperature reading greater than the limit set will cause
an out-of-limit event. If configured for AIN1 and AIN2, this
bit is 1 when AIN1 Input Voltage exceeds VHIGH or VLOW
limits.
D3 1 when external temperature value exceeds TLOW limit. The
default value for this limit register is 0°C, so any external
temperature reading less than or equal to the limit set will
cause an out-of-limit event.
D4 1 indicates a fault (open or short) for the external
temperature sensor.
D5 1 when AIN2 voltage is greater than corresponding VHIGH
limit. 1 when AIN2 voltage is less than or equal to
corresponding VLOW limit.
D6 1 when AIN3 voltage is greater than corresponding VHIGH
limit. 1 when AIN3 voltage is less than or equal to
corresponding VLOW limit.
D7 1 when AIN4 voltage is greater than corresponding VHIGH
limit. 1 when AIN4 voltage is less than or equal to
corresponding VLOW limit.
Interrupt Status 2 Register (Read-Only) [Address = 01h]
This 8-bit read-only register reflects the status of the VDD and
AIN5–AIN8 interrupts that can cause the INT/INT pin to go
active. This register is reset by a read operation provided that
any out-of-limit event has been corrected. It is also reset by a
software reset.
Table 10. Interrupt Status 2 Register
D7
D6
D5
D4 D3 D2 D1 D0
N/A N/A N/A 0* 0* 0* 0* 0*
*Default settings at power-up.
Rev. A | Page 20 of 36
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