ADP3419(2008) Просмотр технического описания (PDF) - ON Semiconductor
Номер в каталоге
Компоненты Описание
производитель
ADP3419 Datasheet PDF : 13 Pages
| |||
ADP3419
THEORY OF OPERATION
The ADP3419 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs. Each
driver is capable of driving a 3 nF load at speeds up to 1 MHz. A
more detailed description of the ADP3419 and its features
follows. Refer to the detailed block diagram in Figure 17.
5V
VDCIN
D1
VCC
5
UVLO
AND BIAS
ADP3419
CROWBAR 4
IN 1
SD 2
DRVLSD 3
OVERLAP
PROTECTION
AND
TIME-OUT
CIRCUIT
BST
10
RBST
+CBST
DRVH
9
Q1
SW
8
VCC
7
GND
DRVL
6
Q2
Figure 17. Detailed Block Diagram of the ADP3419
UNDERVOLTAGE LOCKOUT
The undervoltage lockout (UVLO) circuit holds both MOSFET
driver outputs low during VCC supply ramp-up. The UVLO
logic becomes active and in control of the driver outputs at a
supply voltage of no greater than 1.5 V. The UVLO circuit waits
until the VCC supply has reached a voltage high enough to bias
logic level MOSFETs fully on before releasing control of the
drivers to the control pins.
DRIVER CONTROL INPUT
The driver control input (IN) is connected to the duty ratio
modulation signal of a switch-mode controller. IN can be
driven by 2.5 V to 5.0 V logic. The output MOSFETs are driven
so that the SW node follows the polarity of IN.
LOW-SIDE DRIVER
The low-side driver is designed to drive a ground-referenced
low RDS(ON) N-channel synchronous rectifier MOSFET. The bias
to the low-side driver is internally connected to the VCC supply
and GND. Once the supply voltage ramps up and exceeds the
UVLO threshold, the driver is enabled. When the driver is
enabled, the driver’s output is 180° out of phase with the IN pin.
Table 4 shows the relationship between DRVL and the different
control inputs of the ADP3419.
HIGH-SIDE DRIVER
The high-side driver is designed to drive a floating low RDS(ON)
N-channel MOSFET. The bias voltage for the high-side driver is
developed by an external bootstrap supply circuit, which is
connected between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, CBST. When the ADP3419 is starting up, the SW pin is
at ground, so the bootstrap capacitor charges up to VCC
through D1. Once the supply voltage ramps up and exceeds the
UVLO threshold, the driver is enabled. When IN goes high, the
high-side driver begins to turn on the high-side MOSFET (Q1)
by transferring charge from CBST. As Q1 turns on, the SW pin
rises up to VDCIN, forcing the BST pin to VDCIN + VC(BST), which is
enough gate-to-source voltage to hold Q1 on. To complete the
cycle, Q1 is switched off by pulling the gate down to the voltage
at the SW pin. When the low-side MOSFET (Q2) turns on, the
SW pin is pulled to ground. This allows the bootstrap capacitor
to charge up to VCC again.
When the driver is enabled, the driver’s output is in phase with
the IN pin. Table 4 shows the relationship between DRVH and
the different control inputs of the ADP3419.
OVERLAP PROTECTION CIRCUIT
The overlap protection circuit prevents both main power
switches, Q1 and Q2, from being on at the same time. This is
done to prevent shoot-through currents from flowing through
both power switches and the associated losses that can occur
during their on-off transitions. The overlap protection circuit
accomplishes this by adaptively controlling the delay from Q1’s
turn-off to Q2’s turn-on, and the delay from Q2’s turn-off to
Q1’s turn-on.
To prevent the overlap of the gate drives during Q1’s turn-off
and Q2’s turn-on, the overlap circuit monitors the voltage at the
SW pin and DRVH pin. When IN goes low, Q1 begins to turn
off. The overlap protection circuit waits for the voltage at the
SW and DRVH pins to both fall below 1.6 V. Once both of these
conditions are met, Q2 begins to turn on. Using this method,
the overlap protection circuit ensures that Q1 is off before Q2
turns on, regardless of variations in temperature, supply voltage,
gate charge, and drive current. There is, however, a timeout
circuit that overrides the waiting period for the SW and DRVH
pins to reach 1.6 V. After the timeout period has expired, DRVL
is asserted high regardless of the SW and DRVH voltages. In the
opposite case, when IN goes high, Q2 begins to turn off after a
propagation delay. The overlap protection circuit waits for the
voltage at DRVL to fall below 1.6 V, after which DRVH is
asserted high and Q1 turns on.
Rev. 2 | Page 9 of 13 | www.onsemi.com
Share Link: 