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производитель

AD9517-4ABCPZ-RL7

12-Output Clock Generator with Integrated 1.6 GHz VCO

Analog Devices

AD9517-4ABCPZ-RL7 Datasheet PDF : 80 Pages

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Data Sheet

AD9517-4

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

Table 6.

Parameter

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 1 GHz, Output = 1 GHz

Divider = 1

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

At 10 MHz Offset

At 100 MHz Offset

CLK = 1 GHz, Output = 200 MHz

Divider = 5

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

CLK-TO-LVDS ADDITIVE PHASE NOISE

CLK = 1.6 GHz, Output = 800 MHz

Divider = 2

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

At 10 MHz Offset

At 100 MHz Offset

CLK = 1.6 GHz, Output = 400 MHz

Divider = 4

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

CLK-TO-CMOS ADDITIVE PHASE NOISE

CLK = 1 GHz, Output = 250 MHz

Divider = 4

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

Min Typ Max

−109

−118

−130

−139

−144

−146

−147

−149

−120

−126

−139

−150

−155

−157

−103

−110

−120

−127

−133

−138

−147

−149

−114

−122

−132

−140

−146

−150

−155

−110

−120

−127

−136

−144

−147

−154

Unit

Test Conditions/Comments

Distribution section only; does not include PLL and VCO

Input slew rate > 1 V/ns

dBc/Hz

Input slew rate > 1 V/ns

dBc/Hz

Distribution section only; does not include PLL and VCO

Input slew rate > 1 V/ns

dBc/Hz

Input slew rate > 1 V/ns

dBc/Hz

Distribution section only; does not include PLL and VCO

Input slew rate > 1 V/ns

dBc/Hz

Rev. E | Page 9 of 80

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