28L202A1B Просмотр технического описания (PDF) - Philips Electronics

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производитель

28L202A1B

Dual universal asynchronous receiver/transmitter (DUART)

Philips Electronics 

Philips Semiconductors

Dual universal asynchronous receiver/transmitter

(DUART)

Objective specification

SC28L202

PIN CONFIGURATION FOR 68XXX BUS INTERFACE (INTEL)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SYMBOL

PIN

TYPE

NAME AND FUNCTION

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/M

I Bus Configuration: When low configures the bus interface to the Conditions shown in this table.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ D0–D7

I/O Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the DUART and the

CPU. D0 is the least significant bit.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CSN

I Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on

D0–D7 as controlled by the R/WN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condition.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ R/WN

I Read/Write: Input Signal. When CSN is low R/WN high input a read cycle, when low a write cycle.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IACKN

I Interrupt Acknowledge: Active low input indicates an interrupt acknowledge cycle. Usually asserted by the CPU in

response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DACKN

O Data Transfer Acknowledge: A3–State active –low output asserted in a write, read, or interrupt acknowledge cycle to

indicate proper transfer of data between the CPU and the DUART.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ A0–A3

I Address Inputs: Select the DUART internal registers and ports for read/write operations.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RESETN

I Reset: A low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state,

stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark

(High) state. Sets MR pointer to MR1.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ INTRN

O Interrupt Request: Active–Low, open-drain, output which signals the CPU that one or more of the eight maskable

interrupting conditions are true.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ X1/CLK

I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When

a crystal is used, a capacitor must be connected from this pin to ground (see Figure 7).

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ X2

O Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ pin to ground (see Figure 7). If X1/CLK is driven from an external source, this pin must be left open.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxDA

I Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High; “space” is Low.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxDB

I Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High; “space” is Low.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TxDA

O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the

“mark” condition when the transmitter is disabled, idle or when operating in local loop back mode. “Mark” is High;

“space” is Low.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TxDB

O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the

‘mark’ condition when the transmitter is disabled, idle, or when operating in local loop back mode. ‘Mark’ is High;

‘space’ is Low.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O[7:0]A

I/O General-purpose input and output ports channel A: The character of these pins is controlled by I/OPCR. They

may be inputs or outputs and will present many internal clocks and interrupt signals: RTS, CTS, DTR, DSR etc. All

have change of state detectors and the input is always active.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O[7:0]B

I/O General-purpose input and output ports channel B: The character of these pins is controlled by I/OPCR. They

may be inputs or outputs and will present many internal clocks and interrupt signals: RTS, CTS, DTR, DSR etc. All

have change of state detectors and the input is always active.

ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ VCC

Power Power Supply: +3.3 or +5V supply input 10%

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ VSS

Power Ground

1998 Oct 05

9

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