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28L202A1B

Dual universal asynchronous receiver/transmitter (DUART)

Philips Electronics 

Philips Semiconductors

Dual universal asynchronous receiver/transmitter

(DUART)

Objective specification

SC28L202

The out-of-band flow control is implemented through the

CTSN–RTSN signaling via the I/O ports. The operation of these

hardware handshake signals is described in the receiver and

transmitter discussions.

In-band flow control is a protocol for controlling a remote transmitter

by embedding special characters within the message stream, itself.

Two characters, Xon and Xoff, which do not represent normal

printable character take on flow control definitions when the

Xon/Xoff capability is enabled. Flow control characters received

may be used to gate the channel transmitter on and off. This activity

is referred to as Auto-transmitter mode. To protect the channel

receiver from overrun, fixed fill levels (hardware set at 12

characters) of the RxFIFO may be employed to automatically insert

Xon/Xoff characters in the transmitter’s data stream. This mode of

operation is referred to as auto-receiver mode. Commands issued

by the host CPU via the CR can simulate all these conditions.

Auto-transmitter mode

When a channel receiver pushes an Xoff character into the RxFIFO,

the channel transmitter will finish transmission of the current

character and then stop transmitting. A transmitter so idled can be

restarted by the receipt of an Xon character by the receiver or by a

hardware or software reset. The last option results in the loss of the

un-transmitted contents of the TxFIFO. When operating in this

mode the Command Register commands for the transmitter are not

effective.

While idle data may be written to the TxFIFO and it continue to

present its fill level to the interrupt arbiter and maintains the integrity

of its status registers.

Use of ’00’ as an Xon/Xoff character is complicated by the Receiver

break operation which pushes a ’00’ character on the RxFIFO. The

Xon/Xoff character detectors do not discriminate this case from an

Xon/Xoff character received through the RxD pin.

Note: To be recognized as an Xon or Xoff character, the receiver

must have room in the RxFIFO to accommodate the character. An

Xon/Xoff character that is received resulting in a receiver overrun

does not effect the transmitter nor is it pushed into the RxFIFO,

regardless of the state of the Xon/Xoff transparency bit, MR0 (7).

Xon /Xoff characters

The Xon/Xoff character with errors will be accepted as valid. The

user has the option sending or not sending these characters to the

FIFO. Error bits associated with Xon/Xoff will be stored normally to

the receiver FIFO.

The channel’s transmitter may be programmed to automatically

transmit an Xoff character without host CPU intervention when the

RxFIFO fill level exceeds a fixed limit (12). In this mode it will

transmit an Xon character when the RxFIFO level drops below a

second fixed limit (8). A character from the TxFIFO that has been

loaded into the TxD shift register will continue to transmit.

Character(s) in the TxFIFO that have not been loaded to the

transmitter shift register are unaffected by the Xon or Xoff

transmission. They will be transmitted after the Xon/Xoff activity

concludes.

If the fill level condition that initiates Xon activity negates before the

flow control character can begin transmission, the transmission of

the flow control character will not occur, i.e. either of the following

sequences may be transmitted depending on the timing of the FIFO

level changes with respect to the normal character times:

Character

Character

Xoff

Character

Xon

Character

Hardware keeps track of Xoff characters sent that are not rescinded

by an Xon. This logic is reset by writing MR0 (3) to ’0’. If the user

drops out of Auto-receiver mode while the XISR shows Xoff as the

last character sent the Xon/Xoff logic would not automatically send

the negating Xon.

Host mode

When neither the auto-receiver or auto-transmitter modes are set,

the Xon/Xoff logic is operating in the host mode. In host mode, all

activity of the Xon/Xoff logic is initiated by commands to the CRx.

The Xoff command forces the transmitter to disable exactly as

though an Xoff character had been received by the RxFIFO. The

transmitter will remain disabled until the chip is reset or the CR (7:3)

= 10110 (Xoff resume) command is given. In particular, reception of

an Xon or disabling or re-enabling the transmitter will NOT cause

resumption of transmission. Redundant CRTX—commands, i.e.

CRTXon CRTXon, are harmless, although they waste time. A

CRTXon may be used to cancel a CRTXoff (and vice versa) but both

may be transmitted depending on the command timing with respect

to that of the transmitter state machine.

The kill CRTX command can be used to cleanly terminate any

CRTX commands pending with the minimum impact on the

transmitter.

Note: In no case will an Xon/Xoff character transmission be aborted.

Once the character is loaded into the TX Shift Register, transmission

continues until completion or a chip reset is encountered.

The kill CRTX command has no effect in either of the Auto modes.

Mode control

Xon/Xoff mode control is accomplished via the MR0. Bits 3 and 2

reset to zero resulting in all Xon/Xoff processing being disabled. If

MR0 [2] is set, Xon/Xoff characters received may gate the

transmitter. If MR0 [3] is set, the transmitter will transmit Xon and

Xoff when triggered by attainment of fixed fill levels in the channel

RxFIFO. The MR0 [7] bit also has an Xon/Xoff function control. If

this bit is set, a received Xon or Xoff character is not pushed into the

RxFIFO. If cleared, the power-on and reset default, the received

Xon or Xoff character is pushed onto the RxFIFO for examination by

the host CPU. The MR0 (7) function operates regardless of the

value in MR0 (3:2).

Xon/Xoff Interrupts

The Xon/Xoff logic generates interrupts only in response to

recognizing either of the characters in the XonCR or XoffCR (Xon or

Xoff Character Registers). The transmitter activity initiated by the

Xon/Xoff logic or any CR command does not generate an interrupt.

The character comparators operate regardless of the value in MR0

(3:2). Hence the comparators may be used as general-purpose

character detectors by setting MR0 (3:2)=’00’ and enabling the

Xon/Xoff interrupt in the IMR.

The Dual UART can present the Xon/Xoff recognition event to the

interrupt arbiter for IRQN generation. The IRQN generation may be

masked by setting bit 4 of the Interrupt Mask Register, IMR. The bid

level of an Xon/Xoff recognition event is controlled by the Bidding

Control Register X, BCRX, of the channel. The interrupt status can

be examined in ISR [4]. If cleared, no Xon/Xoff recognition event is

1998 Oct 05

21

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