28L202A1B Просмотр технического описания (PDF) - Philips Electronics

Номер в каталоге

Компоненты Описание

производитель

28L202A1B

Dual universal asynchronous receiver/transmitter (DUART)

Philips Electronics 

Philips Semiconductors

Dual universal asynchronous receiver/transmitter

(DUART)

Objective specification

SC28L202

The time-out mode uses the received data stream to control the

counter. Each time a received character is transferred from the shift

register to the RxFIFO, the counter is restarted. If a new character

is not received before the counter reaches zero count, the counter

ready bit is set, and an interrupt can be generated. This mode can

be used to indicate when data has been left in the RxFIFO for more

than the programmed time limit. Otherwise, if the receiver has been

programmed to interrupt the CPU when the receive FIFO is full, and

the message ends before the FIFO is full, the CPU may not know

there is data left in the FIFO. The CTU and CTL value would be

programmed for just over one character time, so that the CPU would

be interrupted as soon as it has stopped receiving continuous data.

This mode can also be used to indicate when the serial line has

been marking for longer than the programmed time limit. In this

case, the CPU has read all of the characters from the FIFO, but the

last character received has started the count. If there is no new

data during the programmed time interval, the counter ready bit will

get set, and an interrupt can be generated.

Writing the appropriate command to the command register enables

the time-out mode. Writing an ‘Ax’ to CRA or CRB will invoke the

time-out mode for that channel. Writing a ‘Cx’ to CRA or CRB will

disable the time-out mode. The time-out mode should only be used

by one channel at once, since it uses the C/T. If, however, the

time-out mode is enabled from both receivers, the time-out will occur

only when both receivers have stopped receiving data for the

time-out period. CTU and CTL must be loaded with a value greater

than the normal receive character period. The time-out mode

disables the regular START/STOP Counter commands and puts the

ca/T into counter mode under the control of the received data

stream. Each time a received character is transferred from the shift

register to the RxFIFO, the C/T is stopped after 1 C/T clock,

reloaded with the value in CTU and CTL and then restarted on the

next C/T clock. If the C/T is allowed to end the count before a new

character has been received, the counter ready bit, ISR [3], will be

set. If IMR [3] is set, this will generate an interrupt. Receiving a

character after the C/T has timed out will clear the counter ready bit,

ISR [3], and the interrupt. Invoking the ‘Set Time-out Mode On’

command, CRx = ‘Ax’, will also clear the counter ready bit and stop

the counter until the next character is received.

Time Out Mode Caution

When operating in the special time out mode, it is possible to

generate what appears to be a “false interrupt”, i.e. an interrupt

without a cause. This may result when a time-out interrupt occurs

and then, BEFORE the interrupt is serviced, another character is

received, i.e. the data stream has started again. (The interrupt

latency is longer than the pause in the data stream.) In this case,

when a new character has been receiver, the receiver, thereby

withdrawing its interrupt will restart the counter/timer. If, at this time,

the interrupt service begins for the previously seen interrupt, a read

of the ISR will show the “Counter Ready” bit not set. If nothing else

is interrupting, this read of the ISR will return a x’00 character.

CRC Modes and Control

The CRC (Cyclic Redundancy Check) control.

The CRC generator may be programmed to one of four modes as

listed below.

• CRC16: Divisor – x 16 + x 15 + x 2 + 1, dividend preset to zeros.

– The Tx sends the calculated CRC non-inverted.

– The Rx indicates an error if the computed CRC is not equal to 0.

• CRC16: Divisor = x 16 + x 15 + x 2 + 1, dividend preset to ones.

– The Tx sends the calculated CRC non-inverted. The

– Rx indicates an error if the computed CRC is not equal to 0.

• CRC–CCITT: Divisor = x 16 + x 12 + x 5 + 1, dividend preset to zeros

– The Tx sends the calculated CRC non-inverted.

– The Rx indicates an error if the computed CRC is not equal to 0.

• CRC–CCITT: Divisor = x 16 + x 12 + x 5 + 1, dividend preset to ones

– The Tx sends the calculated CRC inverted. The

Rx indicates an error if the computed CRC is not equal to 0xF0B8’.

Data sent to the CRC generator will exclude the stop, parity and

stop bits. The CRC remainder may be read from the CRC registers

if desired.

Interrupt Arbitration

Interrupt Control

The interrupt system determines when an interrupt should be

asserted thorough an arbitration (or bidding) system. This

arbitration is exercised over the several systems within the DUART

that may generate an interrupt. These will be referred to as

“interrupt sources”. There are 18 in all. In general the arbitration is

based on the fill level of the receiver FIFO or the empty level of the

transmitter FIFO. The FIFO levels are encoded into an 8-bit

number, which is concatenated to the channel number and source

identification code. All of this is compared (via the bidding or

arbitration process) to a user defined “threshold”. Whenever a

source exceeds the numerical value of the threshold the interrupt

will be generated.

At the time of interrupt acknowledge (IACKN) the source which has

the highest bid (not necessarily the source that caused the interrupt

to be generated) will be captured in a “Current Interrupt Register”

(CIR). This register will contain the complete definition of the

interrupting source: channel, type of interrupt (receiver, transmitter,

change of state, etc.), and FIFO fill level. The value of the bits in the

CIR are used to drive the interrupt vector and global registers such

that controlling processor may be steered directly to the proper

service routine. A single read operation to the CIR provides all the

information needed to qualify and quantify the most common

interrupt sources.

The interrupt sources for each channel are listed below.

• Transmit FIFO empty level for each channel

• Receive FIFO Fill level for each channel

• Change in break received status for each channel

• Receiver with error for each channel

• Change of state on channel input pins

• Receiver Watch-dog Time out Event

• Xon/Xoff character recognition

• Address character recognition

• Counter/Timer

Associated with the interrupt system are the interrupt mask register

(IMR) and the interrupt status register (ISR) resident in each UART.

Programming of the IMR selects which of the above sources may

enter the arbitration process. Only the bidders in the ISR whose

associated bit in the IMR is set to one (1) will be permitted to enter

the arbitration process. The ISR can be read by the host CPU to

determine all currently active interrupting conditions. For

1998 Oct 05

17

Share Link: