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28L202A1B

Dual universal asynchronous receiver/transmitter (DUART)

Philips Electronics 

Philips Semiconductors

Dual universal asynchronous receiver/transmitter

(DUART)

Objective specification

SC28L202

bits and parity bit (if used) have been assembled, and one half-stop

bit has been detected the receiver loads the byte to the FIFO. The

least significant bit is received first. The data is then transferred to

the Receive FIFO and the RxRDY bit in the SR is set to a 1. This

condition can be programmed to generate an interrupt at OP4 or

OP5 and INTRN. If the character length is less than 8 bits, the most

significant unused bits in the RxFIFO are set to zero.

After the stop bit is detected, the receiver will immediately look for

the next start bit. However, if a non-zero character was received

with the stop bit at a zero level (framing error) and RxD remains Low

for at least another one half bit time after the stop bit was sampled,

then the receiver operates as if a new start bit had been detected. It

then continues assembling the next character.

The error conditions of parity error, framing error, and overrun error

(if any) are strobed into the SR at the received character boundary.

This is just before the RxRDY status bit is set. If a break condition is

detected (RxD is Low for the entire character including the stop bit),

a character consisting of all zeros will be loaded into the RxFIFO

and the received break bit in the SR is set to 1. The RxD input must

return to high for two (2) clock edges of the X1 crystal clock for the

receiver to recognize the end of the break condition and begin the

search for a start bit.

This will usually require a high time of one X1 clock period or 3

X1 edges since the clock of the controller is not synchronous

to the X1 clock.

Receiver Status Bits

There are five (5) status bits that are evaluated with each byte (or

character) received: received break, framing error, parity error,

overrun error, and change of break. The first three are appended to

each byte and stored in the RxFIFO. The last two are not

necessarily related to the byte being received or a byte that is in the

RxFIFO. They are however developed by the receiver state

machine.

The “received break” will always be associated with a zero byte in

the RxFIFO. It means that zero character was a break character

and not a zero data byte. The reception of a break condition will

always set the “change of break” (see below) status bit in the

Interrupt Status Register (ISR).

A framing error occurs when a non-zero character was seen and

that character has a zero in the stop bit position.

The parity error indicates that the receiver-generated parity was not

the same as that sent by the transmitter.

The overrun error occurs when the RxFIFO is full, the receiver shift

register is full and another start bit is detected. At this moment the

receiver has 257 valid characters and the start bit of the 258th has

been seen. At this point the host has approximately 7/16 bit time to

read a byte from the RxFIFO or the overrun condition will be set and

the 258th character will overrun the 257th and the 258th the 259th

and so on until an open position in the RxFIFO is seen. The

fundamental meaning of the overrun is that data has been lost.

Data in the RxFIFO remains valid. The receiver will begin placing

characters in the RxFIFO as soon as a position becomes vacant.

Note: Precaution must be taken when reading an overrun FIFO.

There will be 256th valid characters. Data will begin loading as

soon as the first character is read. The 257th character will

have been received as valid but it will not be known how many

characters were lost between the two characters of the 256th

and 257th reads of the RxFIFO

The “Change of break” means that either a break has been detected

or that the break condition has been cleared. This bit is available in

the ISR. The break change bit being set in the ISR and the received

break bit being set in the SR will signal the beginning of a break. At

the termination of the break condition only the change of break in

the ISR will be set. After the break condition is detected the

termination of the break will only be recognized when the RxD input

has returned to the high state for two successive edges of the 1x

clock; 1/2 to 1 bit time.

The receiver is disabled by reset or via CR commands. A disabled

receiver will not interrupt the host CPU under any circumstance in

the normal mode of operation. If the receiver is in the multi-drop or

special mode, it will be partially enabled and thus may cause an

interrupt. Refer to section on Wake-Up and the register description

for MR1 for more information.

Receiver FIFO

The receiver buffer memory is a 256 byte FIFO with three status bits

appended to each data byte. (The FIFO is then 256 11-bit “words”).

The receiver state machine gathers the bits from the receiver shift

register and the status bits from the receiver logic and writes the

assembled byte and status bits to the RxFIFO. Logic associated

with the FIFO encodes the number of filled positions for presentation

to the interrupt arbitration system. The encoding is always 1 less

than the number of filled positions. Thus, a full RxFIFO will bid with

the value or 255; when empty it will not bit at all; one position

occupied bids with the value 0. An empty FIFO will not bid since no

character is available. Normally RxFIFO will present a bid to the

arbitration system whenever it has one or more filled positions. The

MR2 [3:2 bits allow the user to modify this characteristic so that

bidding will not start until one of four levels (one or more filled, 1/2

filled, 3/4 filled, full) have been reached. As will be shown later this

feature may be used to make slight improvements in the interrupt

service efficiency. A similar system exists in the transmitter.

RxFIFO Status Bits. Status reporting modes

The description below applies to the upper three bits in the “Status

Register” These three bits are not “in the status register”; they are

part of the RxFIFO. The three status bits at the top of the RxFIFO

are presented as the upper three bits of the status register included

in each UART.

The error status of a character, as reported by a read of the SR

(status register upper three bits) can be provided in two ways, as

programmed by the error mode control bit in the mode register:

“Character mode ” or the “Block Mode”. The block mode may be

further modified (via a CR command) to set the status bits as the

characters enter the FIFO or as they are read from the FIFO.

In the ’character’ mode, status is provided on a character by

character basis as the characters are read from the RxFIFO: the

“status” applies only to the character at the top of the RxFIFO – The

next character to be read.

In the ’block’ mode, the status provided in the SR for these three bits

is the logical OR of the status for all characters coming to the top of

the RxFIFO, since the last reset error command was issued. In this

mode each of the status bits stored in the RxFIFO are passed

through a latch as they are sequentially written to the receiver FIFO.

If any of the characters has an error bit set that latch will set and

remain set until it is reset with a “receiver reset” is issued from the

command register or a chip reset is issued. The purpose of this

mode is indicating an error in the data block as opposed to an error

in a character.

1998 Oct 05

15

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