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28L202A1B

Dual universal asynchronous receiver/transmitter (DUART)

Philips Electronics 

Philips Semiconductors

Dual universal asynchronous receiver/transmitter

(DUART)

Objective specification

SC28L202

OVER ALL DESCRIPTION

The SC28L202 is composed of several functional blocks. They are

listed in the approximate order of hierarchy as seen from the pins of

the device.

• Timing Circuits

• Bus interface. 68K or x86 format

• I/O Ports

• UARTS

• Arbitrating Interrupt Structure

• Character & Address Recognition

• Variable FIFO Partition Structure

• Test Modes and Boundary Scan

BRIEF DESCRIPTION OF FUNCTIONAL BLOCKS

Timing Circuits

Crystal Oscillator

The crystal oscillator is the main timing element for the 28L202. It is

nominally set at 14.7456 MHz and may be used to 29.4912 MHz.

The use of an external clock allows all frequencies to 40 MHz.

BRG

The BRG is the baud rate generator, is driven by the crystal input

and generated all of the 24 “fixed” internal baud rates.

Counter-Timer.

The counter-timer provides miscellaneous baud rated, timing

periods and acts as an extra watchdog timer for the for the

receivers. It has 8 clock sources.

Bus Interface

The bus interface operates in “68K” or “x86” format as selected by

the I/M pin. The signals used by this section are the Address, Data

bus, Chip select, read/write, Data acknowledge and Interrupt

acknowledge and Interrupt request. Assertion of DACKN requires

two edges of the X1clk after the assertion of CEN.

I/O ports

Each UART is provided with 8 I/O ports. Each port is equipped with

a change of state detector. The input circuit of these pins is always

active. Under program control the ports my display internal signals

or static logic levels. The functions represented by the I/O ports

include hardware flow control. Modem signals, signals for interrupt

conditions or various internal clocks and timing intervals. Noisy

inputs to the I/O ports are filtered (de-bounced) by a 38.4 KHz clock.

UARTS

The uarts are fully independent, full duplex and provide all normal

asynchronous functions: 5 to 8 data bits, parity odd or even,

programmable stop bit length, false start bit detection. Also

provided are 256 byte FIFOs Xon/Xoff software flow control and

IRDA pulse modulation. The BRG, Counter-timer, or external clocks

provide the baud rates. The receivers and transmitters may operate

in either the “1x” or “16x” modes.

Interrupt Arbitration

The interrupt system uses a highly programmable arbitrating

technique to establish when an interrupt should be presented to the

processor. The advantageous feature of this system is the

presentation of the context of the interrupt. It is presented in both a

current interrupt register and in the interrupt vector. The context of

the interrupt shows the interrupting channel, identifies which of the 8

possible sources in requesting interrupt service and in the case of a

receiver or transmitter gives the current fill level of the FIFO.

The content of the current interrupt register also drives the Global

Registers of the interrupt system. These registers are indirect

addresses (pointers) to the fields describing the internal source

requesting interrupt service.

Programming of Bid Control Registers allows the interrupt level of

any source to be varied at any time over a range of 256 levels.

Character and Address Recognition

The character recognition system is designed as a general system.

There is one for each UART. Each recognition block stores up to

three characters. The recognition is done on a byte boundary and

sets status and interrupt when an recognition event occurs. Each

has four modes of operation.

A subset of the recognition system is Xon/Xoff character recognition

and multi-drop address recognition. If Xon/Xoff or multi-dorp

function is enabled the recognition system passes the information

about the recognition event to the appropriate receiver or transmitter

state machine for execution. In any case the information about a

recognition event is available to the interrupt system and to the

control processor.

FIFO Partitioning and Control

The FIFO memory is implemented in ram. Nominally 1000 bytes of

ram are divided between the four FIFOs of the DUART. The default

partition is 256 (0xFF) bytes for each fifo. Under program control

size of the partition for any a particular FIFO may be varied from 1 to

1024.

The interrupt level for each FIFO is also under program control and

is continuously variable through out the range of the partition. A

small processor controls all of the FIFO reading, writing, interrupting,

flow control signaling, and status reporting.

Test Modes

Three test modes are provided to verify UART function and

processor interface integrity. These are Auto echo, Local Loop

Back, and Remote Loop Back. Through local loop back the

software developer may verify all of the interrupt, flow control; the

hardware designer verifies all of the timing and pin connections. This

information is obtained without any recourse to external test

equipment or terminals.

Boundary scan provides verification of manufacturing process and

to a lesser extent identifies damage that may occur to pins due to

electrical over stress or electrostatic discharge.

DETAILED DESCRIPTIONS

NOTE: For the convenience of the reader some paragraphs in the

following section will be repeated in descriptions of closely linked

functions.

Timing Circuits

Crystal Oscillator

The crystal oscillator operates directly from a crystal, tuned between

14.7456 MHz and 29 4912 MHz connected across the X1/CCLK and

X2 inputs with a minimum of external components. BRG values

listed for the clock select registers correspond to a 14.7456 MHz

1998 Oct 05

11

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