XRT83SH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.4
1.0 CLOCK SYNTHESIZER
In system design, fewer clocks on the network card could reduce noise and interference. Common clock
references such as 8kHz are readily available to network designers. Network cards that support both T1 and
E1 modes must be able to produce 1.544MHz and 2.048MHz transmission data. The XRT83SH314 has a built
in clock synthesizer that requires only one input clock reference by programming CLKSEL[3:0] in the
appropriate global register. A list of the input clock options is shown in Table 1.
TABLE 1: INPUT CLOCK SOURCE SELECT
CLKSEL[3:0]
0h (0000)
1h (0001)
2h (0010)
3h (0011)
4h (0100)
5h (0101)
6h (0110)
7h (0111)
8h (1000)
9h (1001)
Ah (1010)
Bh (1011)
Ch (1100)
Dh (1101)
Eh (1110)
Fh (1111)
INPUT CLOCK REFERENCE
2.048 MHz
1.544MHz
8 kHz
16 kHz
56 kHz
64 kHz
128 kHz
256 kHz
4.096 MHz
3.088 MHz
8.192 MHz
6.176 MHz
16.384 MHz
12.352 MHz
2.048 MHz
1.544 MHz
The single input clock reference is used to generate multiple timing references. The first objective of the clock
synthesizer is to generate 1.544MHz and 2.048MHz for each of the 14 channels. This allows each channel to
operate in either T1 or E1 mode independent from the other channels. The state of the equalizer control bits in
the appropriate channel registers determine whether the LIU operates in T1 or E1 mode. The second objective
is to generate additional output clock references for system use. The available output clock references are
shown in Figure 2.
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